Owner manual
Table Of Contents
- 1. Pin Descriptions
- 2. Characteristics and Specifications
- Recommended Operating Conditions
- Absolute Maximum Ratings
- DAC Analog Characteristics
- Combined Digital and On-Chip Analog Filter Characteristics
- Switching Specifications - Serial Audio Interface
- Digital Interface Characteristics
- Internal Power-On Reset Threshold Voltages
- DC Electrical Characteristics
- 2.1 Digital I/O Pin Characteristics
- 3. Typical Connection Diagram
- 4. Applications
- 5. Combined Digital and On-chip Analog Filter Response Plots
- Figure 10. Single-Speed Stopband Rejection
- Figure 11. Single-Speed Transition Band
- Figure 12. Single-Speed Transition Band (detail)
- Figure 13. Single-Speed Passband Ripple
- Figure 14. Double-Speed Stopband Rejection
- Figure 15. Double-Speed Transition Band
- Figure 16. Double-Speed Transition Band (detail)
- Figure 17. Double-Speed Passband Ripple
- Figure 18. Quad-Speed Stopband Rejection
- Figure 19. Quad-Speed Transition Band
- Figure 20. Quad-Speed Transition Band (detail)
- Figure 21. Quad-Speed Passband Ripple
- 6. Parameter Definitions
- 7. Package Information
- 8. Ordering Information
- 9. Revision History
16 DS895F2
CS4354
When power is first applied, the POR circuit monitors the VA supply voltage to determine when it reaches
a defined threshold, V
on1
. At this time, the POR circuit asserts the internal reset low, resetting all of the
digital circuitry. Once the VA supply reaches the secondary threshold, V
on2
, the POR circuit releases the
internal reset.
When power is removed and the VA voltage reaches a defined threshold, V
off
, the POR circuit asserts the
internal reset low, resetting all of the digital circuitry.
Note: For correct operation of the internal POR circuit, the voltage on VL must rise before or simulta-
neously with VA.
4.8 Initialization
When power is first applied, the DAC enters a reset (low power) state at the beginning of the initialization
sequence. In this state, the AOUTx pins are weakly pulled to ground and FILT+ is connected to GND.
The device will remain in the reset state until V
ON2
is reached. Once V
ON2
is reached, the internal digital
circuitry is reset and the DAC enters a power-down state until MCLK is applied.
Once MCLK is valid, the device enters an initialization state in which the charge pump powers up and charg-
es the capacitors for the negative voltage supply.
Once LRCK is valid, the number of MCLK cycles is counted relative to the LRCK period to determine the
MCLK/LRCK frequency ratio. Next, the device enters the power-up state in which the interpolation filters
and delta-sigma modulators are turned on, the internal voltage reference, FILT+, powers up to normal op-
eration, the analog output pull-down resistors are removed, and power is applied to the output amplifiers.
If a valid SCLK is applied, the device will clock in data according to the applied SCLK. If no SCLK is present,
the device will clock in data using the derived internal SCLK (see Figure 3 on page 9) and will apply the de-
emphasis filter according to Section 4.4.2.1 on page 14.
After this power-up state sequence is complete, normal operation begins and analog output is generated.
If valid MCLK, LRCK, and SCLK are applied to the DAC before V
ON2
is reached, the total time from V
ON2
to the analog audio output from AOUTx is less than 50 ms.
See Figure 9 for a diagram of the device’s states and transition conditions.