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5-V Stereo DAC with 2-V

RMS

Ground-Centered Output

Features

 Advanced multibit delta–sigma modulator

 101 dB A-weighted dynamic range

 –86 dB THD+N

 Single-ended ground-centered analog

architecture

– No DC-blocking capacitors required

– Integrated inverting charge pump

– Filtered line-level outputs

–2V

RMS

full-scale output

 Low-latency digital filtering

 Supports sample rates up to 192 kHz

 24-bit I²S input

 +5-V analog supply with integrated inverting

charge pump and regulator for core logic, and

+1.8-V to +5-V interface power supplies

 50-mW power consumption

 14-pin SOIC, lead-free assembly

Description

The CS4354 is a complete stereo digital-to-analog sys-

tem including digital interpolation, third-order multi-bit

delta–sigma digital-to-analog conversion, digital de-em-

phasis, analog filtering, and on-chip 2 V

RMS

line-level

driver from a 5 V supply.

The advantages of this architecture include ideal differ-

ential linearity, no distortion mechanisms due to resistor

matching errors, no linearity drift over time and temper-

ature, high tolerance to clock jitter, and a minimal set of

external components.

These features are ideal for cost-sensitive, two-channel

audio systems including video game consoles, Blu-Ray

Disc

and DVD players, set-top boxes, digital TVs, and

DAB/DMB devices.

The CS4354 is available in a 14-pin SOIC package in

Commercial (–40°C to +85°C) grade. The CDB4354

Customer Demonstration Board is also available for de-

vice evaluation and implementation suggestions.

Please see “Ordering Information” on page 23 for com-

plete details.

PCM Serial

Audio Port

Level Shifter

I²S Serial

Audio Input

Multibit

Modulator

Interpolation

Filters + HPF

Left Channel

Right Channel

Power-On

Reset

Auto Speed

Mode Detect

Analog Supply (VA)

+5 V

Inverting

Charge

Pump

1.8V reg

-VA

Interface Supply (VL)

+1.8V to +5V

Ground-Centered,

2 Vrms Line Level

Outputs

DAC

Sept '11

DS895F2

CS4354

Summary of content (24 pages)

PAGE 1
CS4354 5-V Stereo DAC with 2-VRMS Ground-Centered Output Features Description  Advanced multibit delta–sigma modulator The CS4354 is a complete stereo digital-to-analog system including digital interpolation, third-order multi-bit delta–sigma digital-to-analog conversion, digital de-emphasis, analog filtering, and on-chip 2 VRMS line-level driver from a 5 V supply.
PAGE 2
CS4354 TABLE OF CONTENTS 1. PIN DESCRIPTIONS ........................................................................................................................... 4 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5 RECOMMENDED OPERATING CONDITIONS .................................................................................... 5 ABSOLUTE MAXIMUM RATINGS .....................................................................
PAGE 3
CS4354 Figure 14. Double-Speed Stopband Rejection .......................................................................................... 20 Figure 15. Double-Speed Transition Band ................................................................................................ 20 Figure 16. Double-Speed Transition Band (detail) .................................................................................... 21 Figure 17. Double-Speed Passband Ripple ...................................................
PAGE 4
CS4354 1. PIN DESCRIPTIONS Pin Name Pin # VL 1 14 -VFILT SDIN 2 13 FLYN MCLK 3 12 FLYP LRCK 4 11 VA SCLK/DEM 5 10 GND GND 6 9 AOUTB FILT+ 7 8 AOUTA Pin Description VL 1 Serial Audio Interface Power (Input) - Positive power for the serial audio interface. SDIN 2 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. MCLK 3 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
PAGE 5
CS4354 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground.(Note 1) Parameters DC power supply Ambient operating temperature (power applied) Analog power Interface power -CSZ Symbol Min Typ Max Units VA VL TA 4.75 1.4 -40 5.0 1.8, 3.3, 5.0 - 5.25 5.25 +85 V V °C Notes: 1. Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits.
PAGE 6
CS4354 DAC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): TA = 25 °C; VA = 5 V, VL = 3.3 V; GND = 0 V; FILT+, -VFILT, and FLYP/N capacitors as shown in Figure 5 on page 12; input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 20 Hz to 20 kHz.
PAGE 7
CS4354 COMBINED DIGITAL AND ON-CHIP ANALOG FILTER CHARACTERISTICS The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Reference level (0 dB) is set at 997 Hz. (Note 11) Parameter Single-Speed Mode - 48 kHz Passband (Note 8) to -0.
PAGE 8
CS4354 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE Parameters Symbol MCLK frequency MCLK duty cycle Min Typ Max Units 7.6 - 55.
PAGE 9
CS4354 LRCK t sclkh t slrs t slrd t sclkl SCLK t sdh t sdlrs SDIN Figure 1. External Serial Clock Mode Input Timing MCLK t mclkf LRCK t sclkr SDIN t sdlrs t sdh * INTERNAL SCLK t sclkw The SCLK pulses shown are internal to the CS4354. Figure 2. Internal Serial Clock Mode Input Timing LRCK MCLK 1 N 2 N *INTERNAL SCLK SDIN * The SCLK pulses shown are internal to the CS4354. N equals MCLK divided by SCLK Figure 3.
PAGE 10
CS4354 DIGITAL INTERFACE CHARACTERISTICS Test conditions (unless otherwise specified): GND = 0 V; all voltages with respect to ground. Parameters 1.8 V VL  5.0 V 1.8 V VL  5.0 V High-level input voltage Low-level input voltage Input leakage current Input capacitance Symbol Min Typ Max Units VIH VIL Iin 0.7xVL - 8 0.3xVL ±10 - V V A pF INTERNAL POWER-ON RESET THRESHOLD VOLTAGES Test conditions (unless otherwise specified): GND = 0 V; all voltages with respect to ground.
PAGE 11
CS4354 DC ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise specified): VA = 5 V, VL = 3.3 V; GND = 0 V; SDIN = 0; all voltages with respect to ground. Parameters Symbol Min Typ Max Units IVA IVL IVA IVL - 10 0.1 0.5 1 50 2.5 60 60 13 0.2 65 - mA mA mA A mW mW dB dB - 3.5 4.9 4.
PAGE 12
CS4354 3. TYPICAL CONNECTION DIAGRAM +5 V 2.2 µF + 0.1 µF VA 11 FILT+ 7 + 2.2 µF CS4354 Digital Audio Processor 3 MCLK 5 SCLK/DEM 4 LRCK 2 SDIN Line Level Out Left & Right AOUTA 470  8 2.2 nF Rext Rext 2.2 nF AOUTB +1.8 V to +5 V 1 9 470  Note 1 VL FLYP 10 12 FLYN 13 -VFILT 14 G ND G ND 0.1 µF + + 2.2 µF Note 1: Capacitors must be C0G or equivalent. 2.2 µF 6 Figure 5.
PAGE 13
CS4354 4. APPLICATIONS 4.1 Ground-Centered Line Outputs An on-chip charge pump creates a negative supply which allows the full-scale output swing to be centered around ground. This eliminates the need for large DC-blocking capacitors which create audible pops at power-on and provides improved low frequency response. See the DAC Analog Characteristics table for the complete specifications of the full-scale output voltage.
PAGE 14
CS4354 4.4 Serial Clock The serial clock controls the shifting of data into the input data buffers. The CS4354 supports both external and internal serial clock generation modes. Refer to Figure 6 for a diagram of the I²S data format. Left C ha nnel LR C K R ig ht C ha n nel SCLK SDIN MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 6.
PAGE 15
CS4354 Gain dB T1=50 µs 0dB T2 = 15 µs -10dB F1 3.183 kHz F2 Frequency 10.61 kHz Figure 7. De-Emphasis Curve, Fs = 44.1 kHz Note: 4.5 De-emphasis is only available in Single-Speed Mode. Internal High-Pass Filter The CS4354 includes an internal digital high-pass filter. This filter prevents a constant digital offset from creating a DC voltage on the analog output pins.
PAGE 16
CS4354 When power is first applied, the POR circuit monitors the VA supply voltage to determine when it reaches a defined threshold, Von1. At this time, the POR circuit asserts the internal reset low, resetting all of the digital circuitry. Once the VA supply reaches the secondary threshold, Von2, the POR circuit releases the internal reset. When power is removed and the VA voltage reaches a defined threshold, Voff, the POR circuit asserts the internal reset low, resetting all of the digital circuitry.
PAGE 17
CS4354 U S E R: A pply P ow er P ow er-O n R eset S tate U S ER : R em ove M C LK P ow er-D ow n State U S ER : A pply M C LK Initialization S tate U S ER : Apply LR C K M C LK/LR C K R atio D etection U S E R : C hange M C LK /LR C K ratio V alid M C LK/LR C K R atio P ow er-U p S tate O utputs M uted U S E R: N o SC LK U S E R : A pplied S C LK S C LK m ode = internal SC LK m ode = external N orm al O peration D e-em phasis Is S electable N orm al O peration D e-em phasis Is D isabled A na
PAGE 18
CS4354 4.9 Recommended Operational Sequences The following sequences are recommended for minimal pops and clicks when transitioning between different states of operation. 4.9.1 Power-Up 1. Turn on power supplies. 2. Wait for power supply voltages to stabilize. 3. Apply the serial port clocks and data. Provide the correct MCLK, LRCK, and SCLK (only in External Serial Clock Mode); please refer to Section 4.
PAGE 19
CS4354 shows the recommended power arrangements with VA and VL connected to clean supplies. It is strongly recommended that a single ground plane be used with the GND pins connected to the common plane; this is important because both pin 6 and pin 10 provide analog ground reference to the CS4354. Should it be necessary to split the ground planes, the CS4354 should be placed entirely in the analog plane.
PAGE 20
CS4354 5. COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSE PLOTS Single−Speed Transition Band 0 0 −20 −20 −40 −40 Amplitude(dB) Amplitude(dB) Single−Speed Stopband Rejection −60 −60 −80 −80 −100 −100 −120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 −120 0.4 1 Figure 10. Single-Speed Stopband Rejection 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 11.
PAGE 21
CS4354 Double−Speed Passband Ripple Double−Speed Transition Band Detail 0.2 0 −1 0.15 −2 0.1 −3 Amplitude(dB) Amplitude(dB) 0.05 −4 −5 −6 0 −0.05 −7 −0.1 −8 −0.15 −9 −10 0.45 −0.2 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 0 Figure 16. Double-Speed Transition Band (detail) 0.05 0.1 0.15 Frequency(normalized to Fs) Quad−Speed Transition Band 0 −20 −20 −40 −40 Amplitude(dB) Amplitude(dB) 0 −60 −60 −80 −80 −100 −100 0.3 0.4 0.
PAGE 22
CS4354 6. PARAMETER DEFINITIONS Dynamic Range The ratio of the full-scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement.
PAGE 23
CS4354 7. PACKAGE INFORMATION 7.1 Dimensions 14L SOIC (150 MIL BODY) PACKAGE DRAWING E H 1 b c D SEATING PLANE  A L e DIM A A1 b C D E e H L  MIN 0.0590 0.0040 0.0138 0.0075 0.3380 0.1520 0.2300 0.0160 0° A1 INCHES NOM 0.050 BSC - MAX 0.0708 0.0098 0.0200 0.0098 0.3440 0.1574 0.2440 0.0350 8° MILLIMETERS NOM 1.270 BSC - MIN 1.397 0.102 0.351 0.190 8.585 3.861 5.842 0.406 0° MAX 1.549 0.249 0.508 0.250 8.738 3.998 6.198 0.889 8° JEDEC #: MS-012 Controling Dimension is Millimeters 7.
PAGE 24
CS4354 9. REVISION HISTORY Release F1 F2 Changes Changed 1.8 V VL  5.0 V to 1.8 V VL  5.0 V for both high- and low-level input voltage parameters in Digital Interface Characteristics section on page 10. Updated MCLK duty cycle specification to 35%/65% from 45%/55% in Switching Specifications - Serial Audio Interface section on page 8. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com.