Manual

12 DS566F1
CS4351
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VL, C
L
=20pF)
Notes:
8. t
spi
only needed before first falling edge of CS after RST rising edge. t
spi
= 0 at all other times.
9. Data must be held for sufficient time to bridge the transition time of CCLK.
10. For F
SCK
< 1 MHz.
Parameter Symbol Min Max Unit
CCLK Clock Frequency f
sclk
-6MHz
RST
Rising Edge to CS Falling t
srs
500 - ns
CCLK Edge to CS
Falling (Note 8) t
spi
500 - ns
CS High Time Between Transmissions t
csh
1.0 - µs
CS Falling to CCLK Edge t
css
20 - ns
CCLK Low Time t
scl
66 - ns
CCLK High Time t
sch
66 - ns
CDIN to CCLK Rising Setup Time t
dsu
40 - ns
CCLK Rising to DATA Hold Time (Note 9) t
dh
17 - ns
Rise Time of CCLK and CDIN (Note 10) t
r2
- 100 ns
Fall Time of CCLK and CDIN (Note 10) t
f2
- 100 ns
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
csh
t
spi
t
srs
RST
Figure 3. Control Port Timing - SPI Format (Write)