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10-Pin, 24-Bit, 192 kHz Stereo D/A Converter

Features

 Multi-bit Delta-Sigma Modulator

 24-bit Conversion

 Automatically Detects Sample Rates up to

192 kHz.

 105 dB Dynamic Range

 -90 dB THD+N

 Low Clock-Jitter Sensitivity

 Single +3.3 or +5 V Power Supply

 Filtered Line-Level Outputs

 On-chip Digital De-emphasis

 Popguard

Technology

 Small 10-pin TSSOP Package

Description

The CS4344 family members (CS4344, CS4345, and

CS4348) are complete, stereo digital-to-analog output

systems including interpolation, multibit D/A conversion

and output analog filtering in a 10-pin package. The

CS4344 family supports major audio data interface for-

mats. Individual devices differ only in the supported

interface format.

The CS4344 family is based on a fourth-order multibit

delta-sigma modulator with a linear analog low-pass fil-

ter. This family also includes autospeed mode detection

using both sample rate and master clock ratio as a

method of auto-selecting sampling rates between 2 kHz

and 200 kHz.

The CS4344 family contains on-chip digital deempha-

sis, operates from a single +3.3 V or +5 V power supply,

and requires minimal support circuitry. These features

are ideal for DVD players & recorders, digital televi-

sions, home theater and set top box products, and

automotive audio systems.

The CS4344 family is available in a 10-pin TSSOP

package in both Commercial (-10 to +85 °C) and Auto-

motive grades (-40 to +85 °C). See Section 8. “Ordering

Information” on page 23 for complete details.

PCM

Serial

Interface

Multibit

Modulator

Interpolation

Filter

Internal

Voltage

Reference

Switched

Capacitor

DAC and

Filter

Serial Audio

Input

Right

Output

Left

Output

Switched

Capacitor

DAC and

Filter

De-emphasis

Multibit

Modulator

Interpolation

Filter

3.3 V or 5 V

JUL ‘13

DS613F2

CS4344/5/8

Summary of content (24 pages)

PAGE 1
CS4344/5/8 10-Pin, 24-Bit, 192 kHz Stereo D/A Converter Features Description  Multi-bit Delta-Sigma Modulator The CS4344 family members (CS4344, CS4345, and CS4348) are complete, stereo digital-to-analog output systems including interpolation, multibit D/A conversion and output analog filtering in a 10-pin package. The CS4344 family supports major audio data interface formats. Individual devices differ only in the supported interface format.
PAGE 2
CS4344/5/8 TABLE OF CONTENTS 1. PIN DESCRIPTIONS .............................................................................................................................. 4 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5 SPECIFIED OPERATING CONDITIONS ............................................................................................... 5 ABSOLUTE MAXIMUM RATINGS .....................................................
PAGE 3
CS4344/5/8 LIST OF FIGURES Figure 1.Output Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 2.Maximum Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 3.External Serial Mode Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Figure 4.Internal Serial Mode Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
CS4344/5/8 1. PIN DESCRIPTIONS 1 10 DEM/SCLK 2 9 VA LRCK 3 8 GND MCLK 4 7 AOUTL VQ 5 6 FILT+ AOUTR Pin Name # SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. 2 De-Emphasis/External Serial Clock Input (Input) - used for deemphasis filter control or external serial clock input. 3 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line.
PAGE 5
CS4344/5/8 2. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltage and TA = 25C.) SPECIFIED OPERATING CONDITIONS (AGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Specified Temperature Range -CZZ -DZZ Symbol Min Nom Max Units VA 4.75 3.00 -10 -40 5.0 3.3 - 5.25 3.
PAGE 6
CS4344/5/8 DAC ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz (Note 1), Fs = 48/96/192 kHz; Test load RL = 3 k, CL = 10 pF (Figure 1). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.) 5 V Nom Parameter Min 3.
PAGE 7
CS4344/5/8 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) See (Note 6) Parameter Symbol Min Typ Max Unit 0 0 - .35 .4992 Fs Fs -.175 - +.01 dB .5465 - - Fs 50 - - dB - 10/Fs - s - - +1.5/+0 +.05/-.25 -.2/-.4 dB dB dB 0 0 - .22 .
PAGE 8
CS4344/5/8 DIGITAL INPUT CHARACTERISTICS Parameters High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Symbol Min Typ Max Units VIH VIL Iin 60% - 8 30% ±10 - V V A pF (% of VA) (% of VA) (Note 7) 7. Iin for LRCK is ±20 A max. POWER AND THERMAL CHARACTERISTICS 5 V Nom Parameters 3.3 V Nom Symbol Min Typ Max Min Typ Max Units IA IA - 22 220 110 1.1 95 50 40 30 150 - - 16 100 53 0.
PAGE 9
CS4344/5/8 SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE Parameters Symbol MCLK Frequency MCLK Duty Cycle Input Sample Rate (Note 11) All MCLK/LRCK ratios combined 256x, 384x, 1024x 256x, 384x 512x, 768x 1152x 128x, 192x 64x, 96x 128x, 192x Fs Min Typ Max Units 0.
PAGE 10
CS4344/5/8 LRCK t sclkh t slrs t slrd t sclkl SCLK t sdh t sdlrs SDATA Figure 3. External Serial Mode Input Timing LRCK t sclkr SDATA t sclkw t sdlrs t sdh *INTERNAL SCLK The SCLK pulses shown are internal to the CS4344/5/8. Figure 4. Internal Serial Mode Input Timing LRCK MCLK 1 N 2 N *INTERNAL SCLK SDATA * The SCLK pulses shown are internal to the CS4344/5/8. N equals MCLK divided by SCLK Figure 5.
PAGE 11
CS4344/5/8 3. TYPICAL CONNECTION DIAGRAM Note* = This circuitry is intended for applications where the CS4344/5/8 connects directly to an unbalanced output of the design. For internal routing applications please see the DAC analog output characteristics for loading limitations. +3.3 V to +5 V + 9 0.1 µF 1 µF VA Note* 1 Audio Data Processor 2 3 SDIN 3.3 µF DEM/SCLK AOUTL Left Audio Output 470 7 + LRCK C 10 k CS4344 CS4345 AOUTR 10 CS4348 3.
PAGE 12
CS4344/5/8 4. APPLICATIONS The CS4344 family accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pin (SDIN). The Left/Right Clock (LRCK) determines which channel is currently being input on SDIN, and the optional Serial Clock (SCLK) clocks audio data into the input data buffer. The CS4344/5/8 differ in serial data formats as shown in Figures 7–9. 4.
PAGE 13
CS4344/5/8 Left Channel LRCK Right Channel SCLK SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 Internal SCLK Mode +5 +4 +3 +2 +1 LSB External SCLK Mode I²S, 16-Bit data and INT SCLK = 32 Fs if MCLK/LRCK = 1024, 512, 256, 128, or 64 I²S, Up to 24-Bit data and INT SCLK = 48 Fs if MCLK/LRCK = 768, 384, 192, or 96 I²S, Up to 24-Bit data and INT SCLK = 72 Fs if MCLK/LRCK = 1152 I²S, up to 24-Bit Data Data Valid on Rising Edge of SCLK Figure 7.
PAGE 14
CS4344/5/8 LRCK Right Channel Left Channel SCLK SDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Internal32SCLK clocks Mode Right Justified, 16-Bit Data INT SCLK = 32 Fs if MCLK/LRCK = 1024, 512, 256, 128, or 64 INT SCLK = 48 Fs if MCLK/LRCK = 768, 384, 192, or 96 INT SCLK = 72 Fs if MCLK/LRCK = 1152 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 External SCLK Mode Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 32 Cycles per LRCK Period Figure 9.
PAGE 15
CS4344/5/8 4.3 De-Emphasis The CS4344 family includes on-chip digital deemphasis. Figure 10 shows the deemphasis curve for Fs equal to 44.1 kHz. The frequency response of the deemphasis curve will scale proportionally with changes in sample rate, Fs. The deemphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for 5 consecutive falling edges of LRCK. This function is available only in the internal serial clock mode . Gain dB T1=50 µs 0dB T2 = 15 µs -10dB F1 3.183 kHz F2 Frequency 10.
PAGE 16
CS4344/5/8 When changing clock ratio or sample rate, it is recommended that zero data (or near zero data) be present on SDIN for at least 10 LRCK samples before the change is made. During the clocking change, the DAC outputs will always be in a zero data state. If no zero audio is present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes to its zero data state.
PAGE 17
CS4344/5/8 4.6 Grounding and Power Supply Decoupling As with any high resolution converter, the CS4344 family requires careful attention to power supply and grounding arrangements to optimize performance. Figure 6 shows the recommended power arrangement with VA connected to a clean +3.3 V or +5 V supply. For best performance, decoupling and filter capacitors should be located as close to the device package as possible with the smallest capacitors closest. 4.
PAGE 18
CS4344/5/8 5. FILTER PLOTS Figure 12. Single-Speed Stopband Rejection Figure 13. Single-Speed Transition Band 0 -1 0.05 -2 0 -3 -0.05 Amplitude dB Amplitude dB -4 -5 -6 -0. 1 -0.15 -7 -0. 2 -8 -0.25 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency (normalized to Fs) 0.52 0.53 0.54 Figure 14. Single-Speed Transition Band 18 0.5 5 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (normalized to Fs) 0.35 0.4 0.45 Figure 15. Single-Speed Passband Ripple 0.
PAGE 19
CS4344/5/8 Figure 16. Double-Speed Stopband Rejection Figure 17. Double-Speed Transition Band 1 0.8 0 0.7 -1 0.6 -2 0.5 Amplitude dB Amplitude dB -3 -4 -5 0.4 0.3 0.2 -6 0.1 -7 -8 0 -9 -0. 1 - 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency (normalized to Fs) 0.52 0.53 0.54 Figure 18. Double-Speed Transition Band 0.55 -0. 2 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (normalized to Fs) 0.35 0.4 0.45 0.5 Figure 19.
PAGE 20
CS4344/5/8 0 0 -10 -10 -20 -30 -20 Amplitude (dB) Amplitude (dB) -40 -50 -60 -30 -40 -70 -50 -80 -60 -90 -100 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 0.9 1 0.35 0.4 Figure 20. Quad-Speed Stopband Rejection 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 0.75 Figure 21. Quad-Speed Transition Band 0 0 -5 -10 -0. 5 -20 Amplitude dB Amplitude (dB) -15 -25 -30 -1 -35 -40 -45 -50 -1. 5 0.4 0.45 0.5 0.55 0.
PAGE 21
CS4344/5/8 6. PARAMETER DEFINITIONS Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement.
PAGE 22
CS4344/5/8 7. PACKAGE DIMENSIONS 10LD TSSOP (3 mm BODY) PACKAGE DRAWING N D E11 c E A2 A  e b SIDE VIEW 1 2 3 A1 L SEATING PLANE END VIEW L1 TOP VIEW DIM A A1 A2 b c D E E1 e L L1  MIN -0 0.0295 0.0059 0.0031 ----0.0157 -0° INCHES NOM -----0.1181 BSC 0.1929 BSC 0.1181 BSC 0.0197 BSC 0.0236 0.0374 REF -- MAX 0.0433 0.0059 0.0374 0.0118 0.0091 ----0.0315 -8° MIN -0 0.75 0.15 0.08 ----0.40 -0° MILLIMETERS NOM -----3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 0.60 0.
PAGE 23
CS4344/5/8 8. ORDERING INFORMATION Product CS4344 CS4345 Description 24-Bit, 192 kHz Stereo D/A Converter Package Pb-Free 10-TSSOP Yes CS4348 8.
PAGE 24
CS4344/5/8 9. REVISION HISTORY Release F1 F2 Changes -Updated passband and frequency response specifications in “Combined Interpolation & On-chip Analog Filter Response” on page 7 -Updated PSRR specification -Updated VIH specification -Updated figures in “Filter Plots” on page 18 -Removed references to CS4346 throughout. -Updated Footnote 1 about dither in “DAC Analog Characteristics” on page 6.