User guide

CS4341
DS298F5 13
SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (SPI™)
Notes: 10. t
spi
only needed before first falling edge of CS after RST rising edge. t
spi
= 0 at all other times.
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For f
sclk
< 1 MHz.
Parameter Symbol Min Max Unit
SPI Mode
CCLK Clock Frequency f
sclk
-6MHz
RST
Rising Edge to CS Falling
t
srs
500 - ns
CCLK Edge to CS
Falling (Note 10)
t
spi
500 - ns
CS
High Time Between Transmissions
t
csh
1.0 - µs
CS
Falling to CCLK Edge
t
css
20 - ns
CCLK Low Time t
scl
-ns
CCLK High Time t
sch
-ns
CDIN to CCLK Rising Setup Time t
dsu
40 - ns
CCLK Rising to DATA Hold Time
(Note 11) t
dh
15 - ns
Rise Time of CCLK and CDIN
(Note 12) t
r2
-100ns
Fall Time of CCLK and CDIN
(Note 12) t
f2
-100ns
1
MCLK
-----------------
1
MCLK
-----------------
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
csh
t
spi
t
srs
RST
Figure 15. Control Port Timing - SPI Mode