Manual

CS4340
18 DS297F3
4.4 De-Emphasis
The device includes on-chip digital de-emphasis. Figure 19 shows the de-emphasis curve for Fs equal to 44.1 kHz.
The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.
Pin 8 is available for de-emphasis control and selects the 44.1 kHz de-emphasis filter. If the Internal Serial Clock is
used, pin 3 is also available for additional de-emphasis control and, in combination with pin 8, selects either the 32,
44.1, or 48 kHz de-emphasis filter. Please see Table 6 for the desired de-emphasis control.
LRCK
SCLK
Left Channel
SDIN
65432107
23 22 21 20 19 18
65432107
23 22 21 20 19 18
32 clocks
0
Right Channel
Figure 17. CS4340 Format 2 - Right Justified, 24-Bit Data
LRCK
SCLK
Left Channel
Right Channel
SDIN
6543210987
15 14 13 12 11 10
6543210987
15 14 13 12 11 10
32 clocks
Figure 18. CS4340 Format 3 - Right Justified, 16-Bit Data
Internal SCLK
External SCLK
DEM1 DEM0 Description DEM0 Description
00
Disabled 0 Disabled
01
44.1 kHz 1 44.1 kHz
10
48 kHz
11
32 kHz
Table 6. De-Emphasis Control
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.183 kHz 10.61 kHz
Figure 19. De-Emphasis Curve