Manual

CS43122
12
2. TYPICAL CONNECTION DIAGRAM
SCLK
Audio
Data
Processor
External Clock
MCLK
AGND
AOUTR+
CS43122
SDATA
VA
AOUTR-
+5.5V
0.1
µ
F
+
Mode
Select
M1
M0
AOUTL-
AOUTL+
DGND
VD
MUTE
Analog
Conditioning
Analog
Conditioning
7
22
24
23
19
20
189
1
15
13
11
12
4
14
5
M2
LRCK
10
+
RST
10
M3
M4
2
3
16
25
.01 µf 10 µf
0.1 µf 100 µf
26
27
VREF
FILT+
FILT-
+5.5V
28
6
21
MUTEC
0.1 µf
8
17
+
+
CMOUT
C/H
µf
10 µf
3.3 - 5.0 V
100 µf
+
.01 µf
+
VD
Figure 4. Typical Connection Diagram