Instruction Manual

82 DS882F1
CS42L73
6.4 Power Control 1 (Address 06h)
6.4.1 Power Down ADC x
Configures the power state of ADC channel x. All the analog front-end circuitry (PreAmp, PGA, etc.) as-
sociated with that channel is powered up or down according to this register bit.
Coupled with the PDN_DMICx controls, these bits also select between the ADC and digital mic inputs and
determine the power state of the Input Path digital processing circuitry. Refer to section “Input Paths” on
page 59 for more details.
6.4.2 Power Down Digital Mic x
Coupled with the PDN_ADCx controls, this control selects between the ADC and digital mic inputs and
determines the power state of the digital mic interface and the Input Path digital processing circuitry. Refer
to sections “Input Paths” on page 59 and “DMIC Interface Powering” on page 60 for more details.
6.4.3 Discharge Filt+ Capacitor
Configures the state of the internal clamp on the FILT+ pin.
Note: This must only be set if PDN = 1b. Discharge time with an external 2.2-µF capacitor on FILT+ is
~10 ms.
6.4.4 Power Down Device
Configures the power state of the entire CS42L73.
Notes:
• After powering up the device (PDN: 1b 0b), all sub-blocks will cease to ignore their indi-
vidual power controls (i.e. will be powered according to their power control programming).
76543210
PDN_ADCB PDN_DMICB PDN_ADCA PDN_DMICA Reserved Reserved DISCHG_FILT PDN
PDN_ADCx ADC Status
0 Powered Up
1 Powered Down
PDN_DMICx Digital Mic Interface Status
0 Power State as per table “Digital Mic Interface Power States” on page 60
1
DISCHG_FILT FILT+ Status
0 FILT+ is not clamped to ground
1 FILT+ is clamped to ground
PDN Device Status
0 Powered Up, as per “Power Control 1 (Address 06h)” on page 82, “Power Control 2 (Address 07h)” on
page 83, and “Power Control 3 and Thermal Overload Threshold Control (Address 08h)” on page 84
1 Powered Down