Instruction Manual

138 DS882F1
CS42L73
14.REVISION HISTORY
Revision Changes
F1
• Removed all references to PDN_LDO.
• Updated Stereo DAC to Headphone Amplifier: High HP power output and Mono DAC to Speakerphone Amplifier: High
output power on page 2.
• Added (Note 4) to Absolute Maximum Ratings on page 20. Added a cross-reference to this note in Section 4.12.1 and
Section 4.12.6.
• Added Analog Output Current Limiter On Threshold specification to DC Electrical Characteristics on page 21.
• Clarified Input Impedance (Note 17), MIC1/MIC2 and Input Impedance (Note 17), LINEINA/LINEINB test conditions on
page 23 as 1 kHz.
• Changed expected input impedance variance in (Note 17) on page 24 to ±20%.
• Updated frequency response, passband, and group delay specifications Stereo-ADC and Dual-Digital-Mic Digital Filter
Characteristics on page 24.
• Updated Mic Bias PSRR in Mic BIAS Characteristics on page 26.
• Updated HP Output full-scale voltage and Power in Serial Port to Stereo HP Output Characteristics on page 27.
• Added Output Impedance to Serial Port to Stereo HP Output Characteristics on page 27.
• Updated Speakerphone output voltage and power characteristics in Serial Port-to-Mono Speakerphone Output
Characteristics on page 31.
• Updated Speakerphone PSRR in Serial Port-to-Mono Speakerphone Output Characteristics on page 31.
• Updated Stereo/Mono DAC Interpolation and On-Chip Digital/Analog Filter Characteristics table on page 33 to separate
EAR/HP/LINE and SPK/SPKLINEOUT specifications.
• Updated frequency response, passband, and group delay specifications in Stereo/Mono DAC Interpolation and On-Chip
Digital/Analog Filter Characteristics on page 33.
• Removed old note 46 (pertaining to DAC high-pass filter).
• Updated MIC2_SDET
high level input voltage specification in Digital Interface Specifications and Characteristics on
page 35.
• Updated DMIC_CLK rise time and DMIC_SD setup and hold time specifications and conditions in Switching
Specifications—Digital Mic Interface on page 37.
• Updated Figure 11 to add markings for 90%/10% and VIH/VIL in Switching Specifications—Digital Mic Interface on
page 37.
• Generalized statement about oversampling at the end of the first paragraph in Section 4.1.1, “Basic Architecture.”
• Added Section 4.4, “Pseudodifferential Outputs.”
• Added Section 4.5. “Class H Amplifier.”
• Added Section 4.6, “DAC Limiter.”
• Added Section 4.7, “Analog Output Current Limiter.”
• Updated wait time for Step 3 in Section 4.12.3, “Power-Down Sequence (xSP to HP/LO).”
• Added step to set the DISCHG_FILT bit to Section 4.12.6, “Final Power-Down Sequence.”
• Added Section 4.17, “Fast Start Mode.”
• Added Section 4.18, “Headphone High-Impedance Mode.”
• Added Section 6.1, “Fast Mode Enable (Address 00h),” Section 6.53, “Fast Mode 1 (Address 7Eh),” and Section 6.54,
“Fast Mode 2 (Address 7Fh).”
• Added note to Section 6.17.1, “Digital Swap/Mono,” register description.
• Corrected register names referred to in the body of Section 6.41.1, “ALC Release Rate for Channels A and B.”
• Updated INL DNL plots in Section 8.1.1 and Section 8.4.3.
• Added Section 8.4.4, “Startup Times.”
• Updated package dimensions formatting and added ccc/ddd positional tolerance values to Section 10.
• Removed the CS42L73-CWZ option from ordering information table and added WLCSP halogen-free statement in
Section 12.