Instruction Manual
122 DS882F1
CS42L73
6.49 Interrupt Mask Register 1 (Address 5Eh)
The bits of this register serve as a mask for the interrupt sources found in Interrupt Status Register 1. If a
mask bit is set, the interrupt is unmasked, meaning that its occurrence affects the INT
pin. If a mask bit is
cleared, the condition is masked, meaning that its occurrence will not affect the INT
pin. The bit positions
align with the corresponding bits in Interrupt Status Register 1.
All the mask bits default to 0b.
6.50 Interrupt Mask Register 2 (Address 5Fh)
The bits of this register serve as a mask for the respective interrupt sources found in Interrupt Status Reg-
ister 2. If a mask bit is set, the interrupt is unmasked, meaning that its occurrence affects the INT
pin. If a
mask bit is cleared, the condition is masked, meaning that its occurrence does not affect the INT
pin. The
bit positions align with the corresponding bits in Interrupt Status Register 2.
All the mask bits default to 0b.
6.51 Interrupt Status Register 1 (Address 60h)
- Read Only
Refer to section “Interrupts” on page 70.
6.51.1 MIC2 Short Detect
- Read Only; not sticky;
or
edge can trigger interrupt
Indicates a short-to-ground condition across the MIC2 microphone module nodes, measured at the
MIC2_SDET
input pin. State transitions are debounced for 20 ms in both the rising and falling directions.
Rising and falling transitions cause an interrupt, if the associated interrupt mask bit is set.
Note: MIC2_BIAS must be enabled (PDN_MIC2_BIAS = 0b and PDN = 0b) before MIC2 Short Detect
occurrences are posted or used for automatic muting.
6.51.2 Thermal Overload Detect
- Read Only; sticky;
edge can trigger interrupt
If thermal sensing is enabled, this bit indicates whether the current junction temperature has exceeded
the thermal overload threshold. This status bit is sticky. Rising-edge state transitions cause an interrupt,
if the associated interrupt mask bit is set.
76543210
Reserved M_MIC2_SDET Reserved M_THMOVLD M_DIGMIXOVFL Reserved M_IPBOVFL M_IPAOVFL
76543210
Reserved Reserved M_VASRC_
DOLK
M_VASRC_DILK M_AASRC_
DOLK
M_AASRC_DILK M_XASRC_
DOLK
M_XASRC_DILK
76543210
Reserved MIC2_SDET Reserved THMOVLD DIGMIXOVFL Reserved IPBOVFL IPAOVFL
MIC2_SDET Pin State
0 No short condition detected
1 Short condition detected
THMOVLD State
0 No thermal overload condition
1 Thermal overload condition detected