Instruction Manual

66 DS773F1
CS42L55
6.33.3 Limiter Soft Ramp Disable
Configures an override of the digital soft ramp setting.
6.34 Status (Address 29h) (Read Only)
For bits [6:0] in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets these bits to 0.
6.34.1 HPDETECT Pin Status (Read Only)
Indicates the status of the HPDETECT pin.
6.34.2 Serial Port Clock Error (Read Only)
Indicates the status of the MCLK to LRCK ratio.
Note: On initial power up and application of clocks, this bit will report ‘1’b as the serial port re-synchro-
nizes.
6.34.3 DSP Engine Overflow (Read Only)
Indicates the over-range status in the DSP data path.
6.34.4 MIXx Overflow (Read Only)
Indicates the over-range status in the PCM mix data path.
LIMSRDIS Limiter Soft Ramp Disable
0 OFF; Limiter Attack Rate is dictated by the DIGSFT (“Digital Soft Ramp” on page 46) setting
1 ON; Limiter volume changes take effect in one step, regardless of the DIGSFT setting.
76543210
HPDETECT SPCLKERR DSPBOVFL DSPAOVFL MIXBOVFL MIXAOVFL ADCBOVFL ADCAOVFL
HPDETECT Pin State
0Low
1High
SPCLKERR Serial Port Clock Status:
0 MCLK/LRCK ratio is valid.
1 MCLK/LRCK ratio is not valid.
Application: “Serial Port Clocking” on page 34
DSPxOVFL DSP Overflow Status:
0 No digital clipping has occurred in the data path after the DSP.
1 Digital clipping has occurred in the data path after the DSP.
MIXxOVFL PCM Overflow Status:
0 No digital clipping has occurred in the data path of the ADC and PCM mix of the DSP.
1 Digital clipping has occurred in the data path of the ADC and PCM mix of the DSP.