User Manual
Table Of Contents
- 1. Pin Descriptions
- 2. Typical Connection Diagram
- 3. Characteristic and Specifications
- Recommended Operating Conditions
- Absolute Maximum Ratings
- Analog Input Characteristics
- ADC Digital Filter Characteristics
- Analog Output Characteristics
- Analog Passthrough Characteristics
- PWM Output Characteristics
- Headphone Output Power Characteristics
- Line Output Voltage Level Characteristics
- Combined DAC Interpolation and onChip Analog FIlter Response
- Switching Specifications - Serial Port
- Switching Specifications - I²C Control Port
- DC Electrical Characteristics
- Digital Interface Specifications and Characteristics
- Power Consumption
- 4. Applications
- 4.1 Overview
- 4.2 Analog Inputs
- 4.3 Analog Outputs
- 4.4 Analog In to Analog Out Passthrough
- 4.5 PWM Outputs
- 4.6 Serial Port Clocking
- 4.7 Digital Interface Formats
- 4.8 Initialization
- 4.9 Recommended Power-up Sequence
- 4.10 Recommended Power-Down Sequence
- 4.11 Required Initialization Settings
- 4.12 Control Port Operation
- 5. Register Quick Reference
- 6. Register Description
- 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only)
- 6.2 Power Control 1 (Address 02h)
- 6.3 Power Control 2 (Address 03h)
- 6.4 Power Control 3 (Address 04h)
- 6.5 Clocking Control (Address 05h)
- 6.6 Interface Control 1 (Address 06h)
- 6.7 Interface Control 2 (Address 07h)
- 6.8 Input x Select: ADCA and PGAA (Address 08h), ADCB and PGAB (Address 09h)
- 6.9 Analog and HPF Control (Address 0Ah)
- 6.10 ADC HPF Corner Frequency (Address 0Bh)
- 6.11 Misc. ADC Control (Address 0Ch)
- 6.12 Playback Control 1 (Address 0Dh)
- 6.13 Miscellaneous Controls (Address 0Eh)
- 6.14 Playback Control 2 (Address 0Fh)
- 6.15 MICx Amp Control:MIC A (Address 10h) and MIC B (Address 11h)
- 6.16 PGAx Vol. and ALCx Transition Ctl.: ALC, PGA A (Address 12h) and ALC, PGA B (Address 13h)
- 6.17 Passthrough x Volume: PASSAVOL (Address 14h) and PASSBVOL (Address 15h)
- 6.18 ADCx Volume Control: ADCAVOL (Address 16h) and ADCBVOL (Address 17h)
- 6.19 ADCx Mixer Volume: ADCA (Address 18h) and ADCB (Address 19h)
- 6.20 PCMx Mixer Volume: PCMA (Address 1Ah) and PCMB (Address 1Bh)
- 6.21 Beep Frequency and On Time (Address 1Ch)
- 6.22 Beep Volume and Off Time (Address 1Dh)
- 6.23 Beep and Tone Configuration (Address 1Eh)
- 6.24 Tone Control (Address 1Fh)
- 6.25 Master Volume Control: MSTA (Address 20h) and MSTB (Address 21h)
- 6.26 Headphone Volume Control: HPA (Address 22h) and HPB (Address 23h)
- 6.27 Speaker Volume Control: SPKA (Address 24h) and SPKB (Address 25h)
- 6.28 ADC and PCM Channel Mixer (Address 26h)
- 6.29 Limiter Control 1, Min/Max Thresholds (Address 27h)
- 6.30 Limiter Control 2, Release Rate (Address 28h)
- 6.31 Limiter Attack Rate (Address 29h)
- 6.32 ALC Enable and Attack Rate (Address 2Ah)
- 6.33 ALC Release Rate (Address 2Bh)
- 6.34 ALC Threshold (Address 2Ch)
- 6.35 Noise Gate Control (Address 2Dh)
- 6.36 Status (Address 2Eh) (Read Only)
- 6.37 Battery Compensation (Address 2Fh)
- 6.38 VP Battery Level (Address 30h) (Read Only)
- 6.39 Speaker Status (Address 31h) (Read Only)
- 6.40 Charge Pump Frequency (Address 34h)
- 7. Analog Performance Plots
- 8. Example System Clock Frequencies
- 9. PCB Layout Considerations
- 10. ADC and DAC Digital Filters
- 11. Parameter Definitions
- 12. Package Dimensions
- 13. Ordering Information
- 14. References
- 15. Revision History
DS680F2 53
CS42L52
3/1/13
Using this bit before the relevant circuitry begins normal operation could cause the change to take
effect immediately, ignoring the FREEZE bit.
6.13.4 HP/Speaker De-emphasis
Configures a 15s/50s digital de-emphasis filter response on the headphone/line and speaker outputs.
6.13.5 Digital Soft Ramp
Configures an incremental volume ramp from the current level to the new level at the specified rate.
Note: When the DIGSFT bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed
to occur with a soft ramp only when
bits 7 and 6 in register 29h are set to ‘00’b.
6.13.6 Digital Zero Cross
Configures when the signal level changes occur for the digital volume controls.
Notes:
1. If the signal does not encounter a zero crossing, the requested volume change will occur after a
timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate).
2. The zero cross function is independently monitored and implemented for each channel.
3. The DIS_LIMSFT bit (“Limiter Soft Ramp Disable” on page 65) is ignored when zero cross is enabled.
4. When the DIGZC bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed to
occur on a zero cross only if bits 7 and 6 in register 29h are set to '00'b
DEEMPHASIS Control Port Status
0 Disabled
1 Enabled
DIGSFT Volume Changes Affected Digital Volume Controls
0 Do not occur with a soft ramp MSTxMUTE (“Master Playback Mute” on page 52),
HPxMUTE, SPKxMUTE (“Playback Control 2 (Address 0Fh)” on page 54),
ADCxVOL[7:0] (“ADCx Volume” on page 57),
AMIXxMUTE, AMIXxVOL[7:0] (“ADC Mixer Channel x Volume” on page 58),
PMIXxMUTE, PMIXxVOL[7:0] (“PCM Mixer Channel x Volume” on page 58),
MSTxVOL[7:0] (“Master Volume Control” on page 63),
HPxVOL[7:0] (“Headphone Volume Control” on page 63),
SPKxVOL[7:0] (“Speaker Volume Control” on page 64),
ALC and Limiter Attack/Release (page 66 to page 68)
Beep Volume (“Beep Volume” on page 61)
1 Occur with a soft ramp
Ramp Rate: 1/8 dB every LRCK cycle
DIGZC Volume Changes Affected Digital Volume Controls
0
Do not occur on a zero cross-
ing
MSTxMUTE (“Master Playback Mute” on page 52),
AMIXxMUTE, AMIXxVOL[7:0] (“ADC Mixer Channel x Volume” on page 58),
PMIXxMUTE, PMIXxVOL[7:0] (“PCM Mixer Channel x Volume” on page 58),
MSTxVOL[7:0] (“Master Volume Control” on page 63),
ALC and Limiter Attack/Release (page 66 to page 68)
Beep Volume (“Beep Volume” on page 61)
1 Occur on a zero crossing