User Manual

DS680F2 21
CS42L52
3/1/13
SWITCHING SPECIFICATIONS - I²C CONTROL PORT
Inputs: Logic 0 = DGND, Logic 1 = VL, SDA C
L
=30pF.
16. Data must be held for sufficient time to bridge the transition time, t
fc
, of SCL.
Parameters Symbol Min Max Unit
SCL Clock Frequency
f
scl
- 100 kHz
RESET Rising Edge to Start
t
irs
550 - ns
Bus Free Time Between Transmissions
t
buf
4.7 - µs
Start Condition Hold Time (prior to first clock pulse)
t
hdst
4.0 - µs
Clock Low time
t
low
4.7 - µs
Clock High Time
t
high
4.0 - µs
Setup Time for Repeated Start Condition
t
sust
4.7 - µs
SDA Hold Time from SCL Falling (Note 16)
t
hdd
0-µs
SDA Setup time to SCL Rising
t
sud
250 - ns
Rise Time of SCL and SDA
t
rc
-1µs
Fall Time SCL and SDA
t
fc
- 300 ns
Setup Time for Stop Condition
t
susp
4.7 - µs
Acknowledge Delay from SCL Falling
t
ack
300 1000 ns
t
buf
t
hdst
t
hdst
t
low
t
r
t
f
t
hdd
t
high
t
sud
t
sust
t
susp
Stop Start
Start
Stop
Repeated
SDA
SCL
t
irs
RST
Figure 4. Control Port Timing - I²C