User Manual

20 DS680F2
CS42L52
3/1/13
SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT C
LOAD
= 15 pF.
14. After powering up the CS42L52, RESET should be held low after the power supplies and clocks are
settled.
15. See “Example System Clock Frequencies” on page 76 for typical MCLK frequencies.
Parameters Symbol Min Max Units
RESET
pin Low Pulse Width (Note 14)
1-ms
MCLK Frequency (Note 15)
(See “Serial Port Clock-
ing” on page 33)
MHz
MCLK Duty Cycle
45 55 %
Slave Mode
Input Sample Rate (LRCK)
F
s
(See “Serial Port Clock-
ing” on page 33)
kHz
LRCK Duty Cycle
45 55 %
SCLK Frequency
1/t
P
-64•F
s
Hz
SCLK Duty Cycle
45 55 %
LRCK Setup Time Before SCLK Rising Edge
t
s(LK-SK)
40 - ns
LRCK Edge to SDOUT MSB Output Delay
t
d(MSB)
-52ns
SDOUT Setup Time Before SCLK Rising Edge
t
s(SDO-SK)
20 - ns
SDOUT Hold Time After SCLK Rising Edge
t
h(SK-SDO)
30 - ns
SDIN Setup Time Before SCLK Rising Edge
t
s(SD-SK)
20 - ns
SDIN Hold Time After SCLK Rising Edge
t
h
20 - ns
Master Mode
Output Sample Rate (LRCK) All Speed Modes
F
s
(See “Serial Port Clock-
ing” on page 33)
Hz
LRCK Duty Cycle
45 55 %
SCLK Frequency SCLK=MCLK mode
1/t
P
- 12.0000 MHz
MCLK=12.0000 MHz
1/t
P
-68•F
s
Hz
all other modes
1/t
P
-64•F
s
Hz
SCLK Duty Cycle
45 55 %
LRCK Edge to SDOUT MSB Output Delay
t
d(MSB)
-52ns
SDOUT Setup Time Before SCLK Rising Edge
t
s(SDO-SK)
20 - ns
SDOUT Hold Time After SCLK Rising Edge
t
h(SK-SDO)
30 - ns
SDIN Setup Time Before SCLK Rising Edge
t
s(SD-SK)
20 - ns
SDIN Hold Time After SCLK Rising Edge
t
h
20 - ns
t
h(SK-SDO)
//
//
//
//
//
//
//
//
t
s(SD-SK)
MSB
MSB
MSB-1
MSB-1
LRCK
SCLK
SDOUT
SDIN
t
d(MSB)
t
s(LK-SK)
t
P
t
h
t
s(SDO-SK)
Figure 3. Serial Audio Interface Timing