User guide

DS679F1 27
CS42L51
4.2 Hardware Mode
A limited feature-set is available when the CODEC powers up in Hardware Mode (see “Recommended Pow-
er-Up Sequence” on page 41) and may be controlled via stand-alone control pins. Table 2 shows a list of
functions/features, the default configuration and the associated stand-alone control available.
Hardware Mode Feature/Function Summary
Feature/Function Default Configuration Stand-Alone Control Note
Power Control CODEC
PGAx
ADCx
DACx
MIC Bias
MICx Pre-amplifier
Powered Up
Powered Up
Powered Up
Powered Up
Powered Down
Powered Down
--
Auto-Detect
Enabled - -
Speed Mode Serial Port Slave
Serial Port Master
Auto-Detect Speed Mode
Single-Speed Mode
--
MCLK Divide
(Selectable) “MCLKDIV2” pin 2
see Section
4.5 on page 38
Serial Port Master / Slave Selection
(Selectable) “M/S” pin 29
see Section
4.5 on page 38
Interface Control ADC
DAC
(Selectable) “I²S/LJ” pin 3
see Section
4.6 on page 40
ADC Volume & Gain Digital Boost
Soft Ramp
Zero Cross
Invert
PGAx
Attenuator
ALC
Noise Gate
Disabled
Disabled
Disabled
Disabled
0 dB
0 dB
Disabled
Disabled
--
ADCx High-Pass Filter
ADCx High-Pass Filter Freeze
Enabled
Continuous DC Subtraction
--
Line/MIC Input Select
AIN1A to PGAA
AIN1B to PGAB
--
DAC Volume & Gain HP Gain
AOUTx Volume
Invert
Soft Ramp
Zero Cross
G = 0.6047
0 dB
Disabled
Enabled
Disabled
--
DAC De-Emphasis
(Selectable) “DEM” pin 4
see Section
on page 34
Signal Processing Engine (SPE) Mix
Beep
Tone Control
Peak Detect and Limiter
Disabled
Disabled
Disabled
Disabled
--
Data Selection
Data Input (PCM) to DAC - -
Channel Mix ADC
DAC
ADCA = L; ADCB = R
PCMA = L; PCMB = R
--
Charge Pump Frequency
(64xFs)/7 - -
Table 2. Hardware Mode Feature Summary