CS4297A CS4297A ® CrystalClear ® SoundFusion™ Audio Codec ‘97 CrystalClear Audio Codec CrystalClearSoundFusion™ SoundFusion™ Audio Codec ’97 ‘97 l AC ’97 2.1 Compatible l Industry or Exceeds the Microsoft PC 99 Audio Performance Requirements l S/PDIF Digital Audio Output l CrystalClear 3D Stereo Enhancement l Meets Features Leading Mixed Signal Technology l 20-bit Stereo Digital-to-Analog Converters Description l 18-bit Stereo Analog-to-Digital Converters The CS4297A is an AC ’97 2.
CS4297A CS4297A TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS .................................................................5 Analog Characteristics ........................................................................................................5 Mixer Characteristics ..........................................................................................................6 Absolute Maximum Ratings .........................................................................................
CS4297A CS4297A 4.10 Stereo Analog Mixer Input Gain Registers (Index 10h - 18h) ................................. 24 4.11 Input Mux Select Register (Index 1Ah) ................................................................... 25 4.12 Record Gain Register (Index 1Ch) ......................................................................... 25 4.13 General Purpose Register (Index 20h) ................................................................... 26 4.14 3D Control Register (Index 22h) ................
CS4297A CS4297A Figure 11. Differential 2 VRMS CD Input ................................................................................35 Figure 12. Differential 1 VRMS CD Input ................................................................................35 Figure 13. Microphone Input ...................................................................................................36 Figure 14. Microphone Pre-amplifier ....................................................................................
CS4297A CS4297A 1. CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS Standard test conditions unless otherwise noted: Tambient = 25° C, AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz; ZAL=100 kΩ/ 1000 pF load, CDL = 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz, 18-bit linear coding for ADC functions, 20-bit linear coding for DAC functions; Mixer registers set for unity gain.
CS4297A CS4297A MIXER CHARACTERISTICS (for CS4297A-KQZ only) Parameter Mixer Gain Range Span Line In, Aux, CD, Video, Mic1, Mic2, Phone, PC Beep Mono Out, Alternate Line Out Line Out Step Size All volume controls except PC Beep PC Beep Min Typ Max Unit - 46.5 46.5 94.5 - dB dB dB - 1.5 3.0 - dB dB Max 6.0 6.0 6.0 1.25 10 15 AVdd+ 0.3 DVdd + 0.
CS4297A CS4297A AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: Tambient = 25° C, AVdd = 5.0 V, DVdd = 3.3 V; CL = 55 pF load.
CS4297A CS4297A BIT_CLK Trst_low Trst2clk RESET# Tvdd2rst# Vdd Figure 1. Power Up Timing BIT_CLK SYNC Tsync2crd CODEC_READY Figure 2. Codec Ready from Startup or Fault Condition BIT_CLK Torise Tifall Tclk_high Tclk_low Tclk_period SYNC Tirise Tsync_high Tifall Tsync_low Tsync_period Figure 3.
CS4297A CS4297A BIT_CLK SDATA_IN Tco SDATA_OUT, SYNC Tisetup Tihold Figure 4. Data Setup and Hold BIT_CLK Slot 1 SDATA_OUT Write to 0x20 Slot 2 Data PR4 Don’t Care Ts2_pdown SDATA_IN SYNC Tsync_pr4 Tsync2clk Figure 5. PR4 Powerdown and Warm Reset RESET# Tsetup2rst SDATA_OUT, SYNC Toff SDATA_IN, BIT_CLK Hi-Z Figure 6.
CS4297A CS4297A 2. GENERAL DESCRIPTION The CS4297A is a mixed-signal serial audio Codec compliant to the Intel® Audio Codec ‘97 Specification, revision 2.1 [1]. It is designed to be paired with a digital controller, typically located on the PCI bus or integrated within the system core logic chip set. The controller is responsible for all communications between the CS4297A and the remainder of the system. The CS4297A contains two distinct functional sections: digital and analog.
CS4297A CS4297A data in its Slot 2. Write operations are similar, with the register index in Slot 1 and the write data in Slot 2 of a SDATA_OUT frame. The function of each input and output frame is detailed in Section 3, AC Link Frame Definition. Individual register descriptions are found in Section 4, Register Interface. 2.4 The input multiplexer controls which analog input is sent to the ADCs.
CS4297A CS4297A PC BEEP BYPASS MUTE VOL MUTE VOL MUTE VOL PHONE VOL PC_BEEP MUTE MAIN D/A CONVERTERS PCM_OUT MIC2 DAC DIRECT MODE Σ Σ Σ ANALOG STEREO OUTPUT MIXER 3D OUTPUT MIXER MASTER VOLUME LINE OUT MUTE OUTPUT BUFFER MUTE OUTPUT BUFFER MUTE OUTPUT BUFFER ALT LINE VOLUME ALT LINE OUT VOL MUTE 3D VOL MUTE VOL AUX MUTE VOL VIDEO MUTE VOL CD VOL LINE BOOST BYPASS BUFFER ANALOG STEREO INPUT MIXER MIC1 DAC MIC SELECT STEREO TO MONO MIXER Σ MONO OUT SELECT VOL
CS4297A CS4297A 3. AC LINK FRAME DEFINITION The AC-link is a bidirectional serial port with data organized into frames consisting of one 16-bit and twelve 20-bit time-division multiplexed slots. The first slot, called the tag slot, contains bits indicating if the CS4297A is ready to receive data (input frame) and which, if any, other slots contain valid data. Slots 1 through 12 contain audio or control/status data.
CS4297A CS4297A 3.1 AC-Link Serial Data Output Frame In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4297A from the AC ’97 controller. Figure 9 illustrates the serial port timing. The PCM playback data being passed to the CS4297A is shifted out MSB first in the most significant bits of each slot. Any PCM data from the AC ’97 controller that is not 20 bits wide should be left justified in its corresponding slot and dithered or zero-padded in the unused bit positions.
CS4297A CS4297A 3.1.2 Command Address Port (Slot 1) Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W RI6 RI5 RI4 RI3 RI2 RI1 RI0 0 0 0 0 0 0 0 0 0 0 0 0 R/W Read/Write. When this bit is ‘set’, a read of the AC ’97 register specified by the register index bits will occur in the AC ’97 2.1 audio codec. When the bit is ‘cleared’, a write will occur.
CS4297A CS4297A 3.2 AC-Link Audio Input Frame In the serial data input frame, data is passed on the SDATA_IN pin from the CS4297A to the AC ’97 controller. The data format for the input frame is very similar to the output frame. Figure 9 on page 13 illustrates the serial port timing. The PCM capture data from the CS4297A is shifted out MSB first in the most significant 18 bits of each slot. The least significant 2 bits in each slot will be ‘cleared’.
CS4297A CS4297A 3.2.3 Bit 19 Status Data Port (Slot 2) 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 RD[15:0] 2 1 0 Reserved Read Data. The RD[15:0] bits contain the register data requested by the controller from the previous read request. All read requests will return the read address in the input Slot 1 and the register data in the input Slot 2 on the following serial data frame. 3.2.
CS4297A CS4297A 3.3 AC-Link Protocol Violation - Loss of SYNC The CS4297A is designed to handle SYNC protocol violations. The following are situations where the SYNC protocol has been violated: • The SYNC signal is not sampled high for exactly 16 BIT_CLK clock cycles at the start of an audio frame. • The SYNC signal is not sampled high on the 256th BIT_CLK clock period after the previous SYNC assertion.
CS4297A CS4297A 4.
CS4297A CS4297A 4.1 D15 0 Reset Register (Index 00h) D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 0 D8 ID8 D7 ID7 D6 0 D5 0 D4 ID4 D3 0 D2 0 D1 0 SE[4:0] Crystal 3D Stereo Enhancement. SE[4:0] = 00110, indicating this feature is present. ID8 18-bit ADC Resolution. The ID8 bit is ‘set’, indicating this feature is present. ID7 20-bit DAC resolution. The ID7 bit is ‘set’, indicating this feature is present. ID4 Headphone Output (Alt Line Out).
CS4297A CS4297A 4.3 D15 Mute Alternate Volume Register (Index 04h) D14 0 D13 ML5 D12 ML4 D11 ML3 D10 ML2 D9 ML1 D8 ML0 D7 0 D6 0 D5 MR5 D4 MR4 D3 MR3 D2 MR2 D1 MR1 D0 MR0 Mute Alternate Mute. Setting this bit mutes the ALT_LINE_OUT_L/R output signals. ML[4:0] Alternate Volume Left. These bits control the left alternate output volume. Each step corresponds to 1.5 dB gain adjustment, with 00000 = 0 dB. The total range is 0 dB to -46.5 dB attenuation.
CS4297A CS4297A 4.5 D15 Mute PC_BEEP Volume Register (Index 0Ah) D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 PV3 D3 PV2 D2 PV1 D1 PV0 D0 0 Mute PC_BEEP Mute. Setting this bit mutes the PC_BEEP input signal. PV[3:0] PC_BEEP Volume Control. The PV[3:0] bits are used to control the gain levels of the PC_BEEP input source to the Input Mixer. Each step corresponds to 3 dB gain adjustment, with 0000 = 0 dB. The total range is 0 dB to -45 dB attenuation. Default 0000h.
CS4297A CS4297A 4.7 D15 Mute Microphone Volume Register (Index 0Eh) D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 20dB D5 0 D4 GN4 D3 GN3 D2 GN2 D1 GN1 D0 GN0 Mute Microphone Mute. Setting this bit mutes the MIC1 or MIC2 signal. The selection of the MIC1 or MIC2 input pin is controlled by the MS bit in the General Purpose Register (Index 20h). GN[4:0] Microphone Volume Control. The GN[4:0] bits are used to control the gain level of the Microphone input source to the Input Mixer.
CS4297A CS4297A 4.8 D15 Mute Stereo Analog Mixer Input Gain Registers (Index 10h - 18h) D14 0 D13 0 D12 GL4 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 0 D6 0 D5 0 D4 GR4 D3 GR3 D2 GR2 D1 GR1 D0 GR0 Mute Stereo Input Mute. Setting this bit mutes the respective input signal, both right and left inputs. GL[4:0] Left Volume Control. The GL[4:0] bits are used to control the gain level of the left analog input source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB.
CS4297A CS4297A 4.9 D15 0 Input Mux Select Register (Index 1Ah) D14 0 D13 0 D12 0 D11 0 D10 SL2 D9 SL1 D8 SL0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 SR2 D1 SR1 D0 SR0 SL[2:0] Left Channel Source. The SL[2:0] bits select the left channel source to pass to the ADCs for recording. See Table 6 for possible values. SR[2:0] Right Channel Source. The SR[2:0] bits select the right channel source to pass to the ADCs for recording. See Table 6 for possible values. Default 0000h.
CS4297A CS4297A 4.11 D15 0 General Purpose Register (Index 20h) D14 0 D13 3D D12 0 D11 0 D10 0 D9 MIX D8 MS D7 LPBK D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 3D 3D Enable. When ‘set’, the 3D bit enables the CrystalClearTM 3D stereo enhancement. This function is not available in DAC Direct Mode (DDM). MIX Mono Output Select. The MIX bit selects the source for the Mono Out output. When ‘set’, the microphone input is selected. When ‘clear’, the stereo-to-mono mixer is selected.
CS4297A CS4297A 4.13 D15 EAPD Powerdown Control/Status Register (Index 26h) D14 PR6 D13 PR5 D12 PR4 D11 PR3 D10 PR2 D9 PR1 D8 PR0 D7 0 D6 0 D5 0 D4 0 D3 REF D2 ANL D1 DAC D0 ADC EAPD External Amplifier Power Down. The EAPD pin follows this bit and is generally used to power down external amplifiers. PR6 Alternate Line Out Powerdown. When ‘set’, the alternate line out buffer is powered down. PR5 Internal Clock Disable.
CS4297A CS4297A 4.14 Extended Audio ID Register (Index 28h) D15 ID1 D14 ID0 D13 0 D12 0 D11 0 D10 0 D9 AMAP D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 VRA ID[1:0] Codec Configuration ID. When ID[1:0] = 00, the CS4297A is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4297A is a secondary audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins. AMAP Audio Slot Mapping. The AMAP bit indicates whether the optional AC ’97 2.
CS4297A CS4297A 4.17 D15 0 AC Mode Control Register (Index 5Eh) D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 D7 DDM AMAP D6 0 D5 SM1 D4 SM0 D3 0 D2 0 D1 0 D0 0 DDM DAC Direct Mode. This bit controls the source to the line and alternate line output drivers. When ‘set’, the L/R DACs directly drive the line and alternate line outputs by bypassing the audio mixer. When ‘clear’, the audio mixer is the source for the line and alternate line outputs. AMAP Audio Slot Mapping.
CS4297A CS4297A 4.19 D15 SPEN S/PDIF Control Register (Index 68h) D14 Val D13 0 D12 Fs D11 L D10 CC6 D9 CC5 D8 CC4 D7 CC3 D6 CC2 D5 CC1 D4 CC0 D3 Emph D2 D1 Copy /Audio D0 Pro SPEN S/PDIF Enable. The SPEN bit enables S/PDIF data transmission on the S/PDIF_OUT pin. The SPEN bit routes the left and right channel data from the AC ’97 controller, the digital mixer, or the digital effects engine to the S/PDIF transmitter block.
CS4297A CS4297A 4.20 Vendor ID1 Register (Index 7Ch) D15 F7 D14 F6 D13 F5 D12 F4 D11 F3 D10 F2 D9 F1 D8 F0 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0 F[7:0] First Character of Vendor ID. With a value of F[7:0] = 43h, these bits define the ASCII ‘C’ character. S[7:0] Second Character of Vendor ID. With a value of S[7:0] = 52h, these bits define the ASCII ‘R’ character. Default 4352h. This register contains read-only data. 4.
CS4297A CS4297A 5. POWER MANAGEMENT 5.1.2 5.1 A Warm Reset allows the AC-link to be reactivated without losing information in the CS4297A registers. A Warm Reset is required to resume from a D3hot state, where the AC-link had been halted yet full power had been maintained. A primary codec Warm Reset is initiated when the SYNC signal is driven high for at least 1 µs and then driven low in the absence of the BIT_CLK clock signal.
CS4297A CS4297A 5.2 Powerdown Controls The Powerdown Control/Status Register (Index 26h) controls the power management functions. The PR[6:0] bits in this register control the internal powerdown states of the CS4297A. Powerdown control is available for individual subsections of the CS4297A by asserting any PRx bit or any combination of PRx bits. Most powerdown states can be resumed by clearing the corresponding PRx bit. Table 10 shows the mapping of the power control bits to the functions they manage.
CS4297A CS4297A PR Bit ADCs PR0 • DACs Mixer Alternate Line Out Analog Reference • • • • • • • • PR1 PR2 PR3 • AC Link Internal Clock Off • • • PR4 PR5 • • • • • PR6 • Table 11. Powerdown PR Function Matrix Power State IDVdd (mA) [DVdd=3.3 V] IDVdd (mA) [DVdd=5 V] IAVdd (mA) Full Power + S/PDIF 1 30.1 49.4 37.9 Full Power 24.5 43.4 37.9 ADCs off (PR0) 21.0 38.1 29.0 DACs off (PR1) 22.1 39.6 31.3 Audio off (PR2) 22.1 39.9 10.7 Vref off (PR3) 18.9 34.
CS4297A CS4297A 6. ANALOG HARDWARE DESCRIPTION The analog line-level input hardware consists of four stereo inputs (LINE_IN_L/R, CD_L/GND/R, VIDEO_L/R, and AUX_L/R), two selectable mono microphone inputs (MIC1 and MIC2), and two mono inputs (PC_BEEP and PHONE). The analog line-level output hardware consists of a mono output (MONO_OUT), and dual stereo line outputs (LINE_OUT_L/R and ALT_LINE_OUT_L/R). This section describes the analog hardware needed to interface with these pins.
CS4297A CS4297A 6.1.3 Microphone Inputs 6.1.4 Figure 13 illustrates an input circuit suitable for dynamic and electret microphones. Electret, or phantom-powered, microphones use the right channel (ring) of the jack for power. The design also supports the recommended advanced frequency response for voice recognition as specified in PC 99. Note the microphone input to the CS4297A has an integrated pre-amplifier.
CS4297A CS4297A 6.1.5 Phone Input MONO_OUT pins require 680 pF to 1000 pF NPO capacitors between the corresponding pin and analog ground. Each analog output is DC-biased up to the Vrefout signal reference, nominally 2.3 V. This requires the outputs be AC-coupled to external circuitry (AC load must be greater than 10 kΩ) or DC coupled to a buffer op-amp biased at Vrefout.
CS4297A CS4297A 6.3 Miscellaneous Analog Signals 6.4 Power Supplies The power supplies providing analog power should be as clean as possible to minimize coupling into the analog section which could degrade analog performance. The analog power pins, AVdd1 and AVdd2, supply power to all the analog circuitry on the CS4297A. The +5 V analog supply should be generated from a linear voltage regulator (7805 type) connected to a +12 V supply.
CS4297A CS4297A 7. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) The S/PDIF digital output is used to interface the CS4297A to consumer audio equipment external to the PC. This output provides an interface for storing digital audio data or playing digital audio data to digital speakers. Figure 20 illustrates the circuits necessary for implementing the IEC-958 optical or consumer interface.
CS4297A CS4297A Vrefout 1000 pF to via NPO Via to +5VA 1 µF 0.1 µF Y5V Via to +5VA AFLT2 AFLT1 AVss1 REFFLT 0.1 µF Y5V AVdd1 Via to Analog Ground AVdd2 Analog Ground Via to Analog Ground AVss2 Digital Ground Via to Digital Ground Pin 1 DVdd1 0.1 µF Y5V DVss1 DVss2 0.1 µF Y5V DVdd2 Via to +5VD or +3.3VD Via to +5VD or +3.3VD Figure 21.
CS4297A CS4297A S/PDIF_OUT EAPD ID1# ID0# NC NC AVss2 ALT_LINE_OUT_R NC ALT_LINE_OUT_L AVdd2 MONO_OUT 9.
CS4297A CS4297A Audio I/O PC_BEEP - Analog Mono Source, Input, Pin 12 The PC_BEEP input is intended to allow the PC system POST (Power On Self-Test) tones to pass through to the audio subsystem. The PC_BEEP input has two connections: the first connection is to the analog output mixer, the second connection is directly to the LINE_OUT stereo outputs. While the RESET# pin is actively being asserted and the BCFG pin is left floating, the PC_BEEP bypass path to the LINE_OUT outputs is enabled.
CS4297A CS4297A VIDEO_L, VIDEO_R - Analog Video Audio Source, Inputs, Pins 16 and 17 These inputs form a stereo input pair to the CS4297A. It is intended to be used for the audio signal output of a video device. The maximum allowable input is 1 VRMS (sinusoidal). These inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry.
CS4297A CS4297A Analog Reference, Filters, and Configuration REFFLT - Internal Reference Voltage, Input, Pin 27 This signal is the voltage reference used internal to the CS4297A. A 0.1 µF and a 1.0 µF (must not be larger than 1 µF) capacitor with short, wide traces must be connected to this pin. No other connections should be made to this pin. Vrefout - Voltage Reference, Output, Pin 28 All analog inputs and outputs are centered around Vrefout, nominally 2.3 Volts.
CS4297A CS4297A AC-Link RESET# - AC ’97 Chip Reset, Input, Pin 11 This active low signal is the asynchronous Cold Reset input to the CS4297A. The CS4297A must be reset before it can enter normal operating mode. SYNC - AC-Link Serial Port Sync pulse, Input, Pin 10 This signal is the serial port timing signal for the AC-link. Its period is the reciprocal of the maximum sample rate, 48 kHz. The signal is generated by the controller, synchronous to BIT_CLK.
CS4297A CS4297A 10. PARAMETER AND TERM DEFINITIONS AC ’97 Specification Refers to the Audio Codec ’97 Component Specification Ver 2.1 published by the Intel® Corporation [6]. AC ’97 Controller or Controller Refers to the control chip which interfaces to the audio codec AC-link. This has been also called DC ’97 for Digital Controller ’97 [6]. AC ’97 Registers or Codec Registers Refers to the 64-field register map defined in the AC ’97 Specification.
CS4297A CS4297A Interchannel Isolation The amount of 1 kHz signal present on the output of the grounded AC-coupled line input channel with 1 kHz, 0 dB, signal present on the other line input channel. Units are in dB. Line-level Refers to a consumer equipment compatible, voltage driven interface. The term implies a low driver impedance and a minimum 10 kΩ load impedance. Paths A-D: Analog in, through the ADCs, onto the serial link. D-A: Serial interface inputs through the DACs to the analog output.
2 1 PHONO-1/8 J7 4 2.2K +5VA 1uF Y5V AGND AGND Y5V C25 AGND 28 1uF + C30 DGND AGND X7R 0.1uF C27 1000pF NPO C26 1000pF NPO AGND X7R 0.01uF Y1 NPO 1000pF C29 CS4297A C6 ELEC 10uF C34 +5VD S/PDIF_OUT nc7 nc6 nc5 ID1# ID0# EAPD BCFG MONO_OUT ALT_LINE_OUT_L ALT_LINE_OUT_R LINE_OUT_L LINE_OUT_R RESET# SYNC SDATA_IN SDATA_OUT BIT_CLK R7 1 2 5 AGND 24.576 MHz (50 PPM) DGND NPO 22pF Figure 23.
CS4297A CS4297A 12. REFERENCES 1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997 http://www.cirrus.com/products/papers/meas/meas.html 2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998 3) Cirrus Logic, AN22: Overview of Digital Audio Interface Data Structures, Version 2.
CS4297A CS4297A 13. PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING E E1 D D1 1 e B ∝ A A1 L DIM A A1 B D D1 E E1 e* L MIN --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000° ∝ * Nominal pin pitch is 0.50 mm INCHES NOM 0.055 0.004 0.009 0.354 0.28 0.354 0.28 0.020 0.24 4° MAX 0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000° MIN --0.05 0.17 8.70 6.90 8.70 6.90 0.40 0.45 0.00° MILLIMETERS NOM 1.40 0.10 0.22 9.0 BSC 7.0 BSC 9.0 BSC 7.0 BSC 0.50 BSC 0.60 4° MAX 1.60 0.15 0.27 9.30 7.
CS4297A • Notes • DS318PP6 51
CS4297A 52 DS318PP6
