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Cirrus Logic, Inc.

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CS4271

24-Bit, 192 kHz Stereo Audio CODEC

D/A Features

! High Performance

– 114 dB Dynamic Range

– -100 dB THD+N

! Up to 192 kHz Sampling Rates

! Differential Analog Architecture

! Volume Control with Soft Ramp

– 1 dB Step Size

– Zero Crossing Click-free Transitions

! Selectable Digital Filters

– Fast and Slow Roll Off

! ATAPI Mixing Functions

! Selectable Serial Audio Interface Formats

– Left Justified up to 24-bit

–I

S up to 24-bit

– Right Justified 16-, 18-, 20-, and 24-Bit

! Control Output for External Muting

! Selectable 50/15 µs De-emphasis

A/D Features

! High Performance

– 108 dB Dynamic Range

– -98 dB THD+N

! Up to 192 kHz Sampling Rates

! Single-Ended Analog Architecture

! Multi-bit Delta Sigma Conversion

! High-pass Filter or DC Offset Calibration

! Low-Latency Digital Anti-alias Filtering

! Automatic Dithering of 16-bit Data

! Selectable Serial Audio Interface Formats

– Left Justified up to 24-bit

–I

S up to 24-bit

System Features

! Direct Interface with 5V to 2.5V Logic Levels

! Internal Digital Loopback

! On-chip Oscillator

! Stand-Alone or Control Port Functionality

2.5 V to 5 V

Left and

Right Mute

Controls

∆Σ Modulator

Low-Latency

Anti-Alias Filter

External

Mute Control

Configuration

Internal Voltage

Reference

Internal

Oscillator

Volume

Control

Mixer

Selectable

Interpolation

Filter

Selectable

Interpolation

Filter

Reset

Left

Differential

Output

Right

Differential

Output

Switched Capacitor

DAC and Filter

Multibit

Oversampling

ADC

Multibit

Oversampling

ADC

Low-Latency

Anti-Alias Filter

High Pass Filter &

DC Offset Calibration

High Pass Filter &

DC Offset Calibration

PCM Serial Interface / Loopback

Left Input

Right Input

Volume

Control

Level TranslatorLevel Translator

Serial

Audio

Input

Serial

Audio

Output

3.3 V to 5 V 5 V

Hardware or

C/SPI

Control Data

Switched Capacitor

DAC and Filter

AUGUST '05

DS592F1

Summary of content (53 pages)

PAGE 1
CS4271 24-Bit, 192 kHz Stereo Audio CODEC D/A Features A/D Features ! High ! High Performance – 108 dB Dynamic Range – -98 dB THD+N – 114 dB Dynamic Range – -100 dB THD+N ! Up to 192 kHz Sampling Rates Analog Architecture ! Multi-bit Delta Sigma Conversion ! High-pass Filter or DC Offset Calibration ! Low-Latency Digital Anti-alias Filtering ! Automatic Dithering of 16-bit Data ! Selectable Serial Audio Interface Formats ! Up to 192 kHz Sampling Rates ! Differential Analog Architecture ! Volume Co
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CS4271 Stand-Alone Mode Feature Set General Description ! System Features – Serial Audio Port Master or Slave Operation – Internal Oscillator for Master Clock The CS4271 is a high-performance, integrated audio CODEC. The CS4271 performs stereo analog-to-digital (A/D) and digital-to-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 192 kHz. ! D/A Features – Auto-mute on Static Samples – 44.
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CS4271 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE MODE ............................................................................. 5 2. PIN DESCRIPTIONS - STAND-ALONE MODE ....................................................................... 7 3. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 9 SPECIFIED OPERATING CONDITIONS ................................................................................. 9 ABSOLUTE MAXIMUM RATINGS .....
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CS4271 6.1 SPI Mode ......................................................................................................................... 35 6.2 I²C Mode .......................................................................................................................... 36 7. REGISTER QUICK REFERENCE .......................................................................................... 37 8. REGISTER DESCRIPTION ..................................................................................
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CS4271 1.
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CS4271 Pin Name XTO XTI # 1,2 Pin Description Crystal Connections (Input/Output) - I/O pins for an external crystal which may be used to generate MCLK. See “Crystal Applications (XTI/XTO)” on page 24 or “Crystal Applications (XTI/XTO)” on page 27. MCLK 3 Master Clock (Input/Output) -Clock source for the delta-sigma modulators. See “Crystal Applications (XTI/XTO)” on page 24 or “Crystal Applications (XTI/XTO)” on page 27.
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CS4271 2.
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CS4271 Pin Name XTO XTI # Pin Description Crystal Connections (Input/Output) - I/O pins for an external crystal which may be used to generate the 1,2 master clock. See “Crystal Applications (XTI/XTO)” on page 24 or “Crystal Applications (XTI/XTO)” on page 27. MCLK 3 Master Clock (Input/Output) -Clock source for the delta-sigma modulators. See “Crystal Applications (XTI/XTO)” on page 24 or “Crystal Applications (XTI/XTO)” on page 27.
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CS4271 3. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.) SPECIFIED OPERATING CONDITIONS (AGND = 0 V; all voltages with respect to ground.
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CS4271 DAC ANALOG CHARACTERISTICS - COMMERCIAL GRADE Parameter Symbol (Notes 3 to 7) Min Typ Max Unit 108 105 - 114 111 94 - dB dB dB - -100 -91 -51 -94 -45 dB dB dB - 114 - dB - 100 - dB - 0.1 - dB - 100 - ppm/°C VFS 0.91xVA 0.96xVA 1.
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CS4271 DAC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE Parameter Symbol (Notes 3 to 7) Min Typ Max Unit 106 103 - 114 111 94 - dB dB dB - -100 -91 -51 -92 -43 dB dB dB - 114 - dB - 100 - dB - 0.1 - dB - 100 - ppm/°C VFS 0.91xVA 0.96xVA 1.
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CS4271 DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (Note 12) Parameter Single Speed Mode - 48 kHz Passband (Note 9) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 11) (Relative to 1kHz) Double Speed Mode - 96 kHz Passband (Note 9) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Quad Speed Mode - 192 kHz Passband (Note 9) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay 12 to -0.
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CS4271 DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (cont) (Note 12) Parameter Single Speed Mode - 48 kHz Passband (Note 9) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 11) (Relative to 1 kHz) Double Speed Mode - 96 kHz Passband (Note 9) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Quad Speed Mode - 192 kHz Passband (Note 9) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Slow
PAGE 14
CS4271 ADC ANALOG CHARACTERISTICS - COMMERCIAL GRADE Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave.
PAGE 15
CS4271 ADC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave.
PAGE 16
CS4271 ADC DIGITAL FILTER CHARACTERISTICS (Note 17) Parameter Symbol Min Typ Max Unit 0 - 0.47 Fs - - ±0.035 dB 0.58 - - Fs Single Speed Mode Passband (-0.1 dB). (Note 15) Passband Ripple. Stopband. (Note 15) Stopband Attenuation. -95 - - dB - 12/Fs - s (Note 15) 0 - 0.45 Fs - - ±0.035 dB (Note 15) 0.68 - - Fs -92 - - dB - 9/Fs - s 0 - 0.24 Fs - - ±0.035 dB 0.78 - - Fs Group Delay. tgd Double Speed Mode Passband (-0.1 dB).
PAGE 17
CS4271 DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Master Mode) Parameter Symbol Min Typ Max Unit VA VL,VD = 5 V VL,VD = 3.3 V IA ID ID - 45 41.5 24 53 49 28 mA mA mA VA VL,VD=5 V IA ID - 0.025 1.76 - mA mA VL, VD=5 V VL, VD = 3.3 V (Power-Down Mode) - - 433 305 9 510 358 - mW mW mW PSRR - 60 - dB VQ - 0.
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CS4271 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF) Parameter Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Symbol Min Typ Max Unit Fs Fs Fs 4 50 100 - 50 100 200 kHz kHz kHz MCLK Specifications MCLK Frequency (note 20) Stand-Alone Mode Control Port Mode fmclk fmclk 1.024 1.024 - 25.600 51.
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CS4271 LRCK O utput t slr SCLK O utput t sdo SDO UT t t sdis sdih SDIN Figure 1. Master Mode Serial Audio Port Timing LRCK Input t t sclkh slr t sclkl SCLK Input t t sdo sclkw SDOUT t sdis t sdih SDIN Figure 2.
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CS4271 Left Channel LRCK Right Channel SCLK SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 3. Format 0, Left Justified up to 24-Bit Data Left Channel LRCK Right Channel SCLK SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 4.
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CS4271 SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT (Inputs: logic 0 = AGND, logic 1 = VL) Parameter Symbol Min Max Unit SCL Clock Frequency. fscl - 100 KHz RST Rising Edge to Start. tirs 500 - ns Bus Free Time Between Transmissions. tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse). thdst 4.0 - µs Clock Low time. tlow 4.7 - µs Clock High Time. thigh 4.0 - µs Setup Time for Repeated Start Condition. tsust 4.
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CS4271 SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: logic 0 = AGND, logic 1 = VL) Parameter Symbol Min Max Unit CCLK Clock Frequency. fsclk - 6 MHz RST Rising Edge to CS Falling. tsrs 500 - ns tspi 500 - ns CS High Time Between Transmissions. tcsh 1.0 - µs CS Falling to CCLK Edge. tcss 20 - ns CCLK Low Time. tscl 82 - ns CCLK High Time. tsch 82 - ns CDIN to CCLK Rising Setup Time. tdsu 40 - ns SPI Mode CCLK Edge to CS Falling.
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CS4271 4. TYPICAL CONNECTION DIAGRAM +5 V * Only one must be used. See "Grounding and Power Supply Decoupling." ∗ 5.1 Ω 0.1 µF 1 µF 0.1 µF 1 µF * +5 V to 3.3 V * Not to exceed 1 µF. VA FILT+ 47 µF ¤ See "Master/Slave Mode Selection". VD VL +5 V to 2.5 V 0.1 µF 0.1 µF AGND 1 µF ∗ CS4271 1 µF ¤ 47 kΩ 0.
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CS4271 5. APPLICATIONS 5.1 Stand-Alone Mode 5.1.1 Recommended Power-Up Sequence 1) When using the CS4271 with an external MCLK, hold RST low until the power supply, MCLK, and LRCK are stable. When using the CS4271 with internally generated MCLK, hold RST low until the power supply is stable. 2) Bring RST high. If the internally generated MCLK is being used, it will appear on the MCLK pin prior to 1 ms from the release of RST. 5.1.
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CS4271 5.1.3.2 Clock Ratio Selection Depending on the use of an external crystal, or whether the CS4271 is in Master or Slave Mode, different MCKL/LRCK and SCLK/LRCK ratios may be used. These ratios are shown in the Tables 3 and 4 below. Table 3.
PAGE 26
CS4271 5.1.4 16-Bit Auto-Dither The CS4271 will auto-configure to output properly dithered 16-bit data when placed in Slave Mode and a 32x SCLK to LRCK ratio is used. In this configuration, one half of a bit of dither is added to the LSB of the 16-bit word. This applies only to the serial audio output of the ADC and will not affect DAC performance. See Figure 9. 1 6 -B it W o rd 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ½ B it D ith e r Figure 9. ADC 16-Bit Auto-Dither 5.1.
PAGE 27
CS4271 5.2 Control Port Mode 5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode 1) When using the CS4271 with an external MCLK, hold RST low until the power supply, MCLK, and LRCK are stable. When using the CS4271 with internally generated MCLK, hold RST low until the power supply is stable. In this state, the Control Port is reset to its default settings. 2) Bring RST high. The device will remain in a low power state and the control port will be accessible.
PAGE 28
CS4271 Table 7. Crystal Frequencies Mode Crystal Frequency Single Speed 512 x Fs Double Speed 256 x Fs Quad Speed 128 x Fs To operate the CS4271 with an externally generated MCLK signal, no crystal should be used, XTI should be connected to ground and XTO should be left unconnected. In this configuration, MCLK is an input and must be driven externally with an appropriate speed clock. 5.2.3.
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CS4271 Table 9.
PAGE 30
CS4271 5.2.4 Internal Digital Loopback In Control Port Mode, the CS4271 supports an internal digital loopback mode in which the output of the ADC is routed to the input of the DAC. This mode may be activated by setting the LOOP bit in the Mode Control 2 register (07h). When this bit is set, the status of the DAC_DIF(2:0) bits in register 01h will be disregarded by the CS4271.
PAGE 31
CS4271 A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS4271. 5.2.8 Interpolation Filter To accommodate the increasingly complex requirements of digital audio systems, the CS4271 incorporates selectable interpolation filters for each mode of operation. Fast and slow roll-off filters are available in each of Single, Double, and Quad Speed modes.
PAGE 32
CS4271 5.4 5.4.1 Analog Connections Input Connections The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n × 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to Figure 12 for a recommended analog input buffer that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators.
PAGE 33
CS4271 5.4.2 Output Connections The recommended output filter configuration is shown in Figure 14. This filter configuration accounts for the normally differing AC loads on the AOUT+ and AOUT- differential output pins. It also shows an AC coupling configuration which minimizes the number of required AC coupling capacitors.
PAGE 34
CS4271 5.5 Mute Control The Mute Control pins become active during power-up initialization, reset, muting, if the MCLK to LRCK ratio is incorrect, and during power-down. The Auto-Mute function causes the MUTEC pin corresponding to an individual channel to activate following the reception of 8192 consecutive audio samples of static 0 or -1 on the respective channel. A single sample of non-zero data on this channel will cause the MUTEC pin to deactivate.
PAGE 35
CS4271 6. CONTROL PORT INTERFACE The Control Port is used to load all the internal settings of the CS4271. The operation of the Control Port may be completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the Control Port pins should remain static if no operation is required. The Control Port has 2 modes: SPI and I²C, with the CS4271 operating as a slave to control messages in both modes. If I²C operation is desired, AD0/CS should be tied to VA or AGND.
PAGE 36
CS4271 6.2 I²C Mode In I²C mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 18. There is no CS pin. Pin AD0 forms the partial chip address and should be tied to VA or AGND as required. The upper 6 bits of the 7-bit address field must be 001000. To communicate with the CS4271, the LSB of the chip address field, which is the first byte sent to the CS4271, should match the setting of the AD0 pin.
PAGE 37
CS4271 7. REGISTER QUICK REFERENCE This table shows the register names and their associated default values.
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CS4271 8. REGISTER DESCRIPTION ** All registers are read/write in I²C mode and write only in SPI mode, unless otherwise noted** 8.1 Mode Control 1 - Address 01h 7 M1 8.1.1 6 M0 5 Ratio1 4 Ratio0 3 M/S 2 DAC_DIF2 1 DAC_DIF1 0 DAC_DIF0 Functional Mode (Bits 7:6) Function: Selects the required range of input sample rates. Table 11. Functional Mode Selection 8.1.
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CS4271 8.2 DAC Control - Address 02h 7 AMUTE 8.2.1 6 FILT_SEL 5 DEM1 4 DEM0 3 RMP_UP 2 RMP_DN 1 INV_A 0 INV_B Auto-Mute (Bit 7) Function: When set, enables the Auto-Mute function. See “Auto-Mute” on page 30. 8.2.2 Interpolation Filter Select (Bit 6) Function: This Function allows the user to select whether the Interpolation Filter has a fast or slow roll off. When set, this bit selects the slow roll off filter, when cleared it selects the fast roll off filter.
PAGE 40
CS4271 8.2.4 Soft Volume Ramp-Up After Error (Bit 3) Function: An un-mute will be performed after executing a filter mode change, after a MCLK/LRCK ratio change or error, and after changing the Functional Mode. When this bit is set, this un-mute is effected, similar to attenuation changes, by the Soft and ZeroCross bits in the DAC Volume & Mixing Control register. When cleared, an immediate un-mute is performed in these instances.
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CS4271 itored and implemented for each channel. See Table 14 on page 41. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing.
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CS4271 Table 15. ATAPI Decode ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 8.4 ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 AOUTA MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] AOUTB MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] DAC Channel A Volume Control - Address 04h See 8.5 DAC Channel B Volume Control - Address 05h 8.
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CS4271 8.6 ADC Control - Address 06h 7 Reserved 8.6.1 6 Reserved 5 Dither16 4 ADC_DIF 3 MUTEA 2 MUTEB 1 HPFDisableA 0 HPFDisableB Dither for 16-Bit Data (Bit 5) Function: When set, this bit activates the Dither for 16-Bit Data feature as described in “Dither for 16-Bit Data” on page 30. 8.6.2 ADC Digital Interface Format (Bit 4) Function: The required relationship between LRCK, SCLK and SDOUT for the ADC is defined by the ADC Digital Interface Format.
PAGE 44
CS4271 8.7.3 Freeze (Bit 2) Function: This function allows modifications to the control port registers without the changes taking effect until FREEZE is disabled. To make multiple changes in the Control Port registers take effect simultaneously, set the FREEZE bit, make all register changes, then clear the FREEZE bit. 8.7.4 Control Port Enable (Bit 1) Function: This bit is cleared by default, allowing the device to power-up in Stand-Alone Mode. Control Port Mode can be accessed by setting this bit.
PAGE 45
CS4271 9. PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement.
PAGE 46
CS4271 10.PACKAGE DIMENSIONS 28L TSSOP (4.4 mm BODY) PACKAGE DRAWING N D E11 A2 E A ∝ e b2 SIDE VIEW A1 L END VIEW SEATING PLANE 1 2 3 TOP VIEW DIM A A1 A2 b D E E1 e L ∝ MIN -0.002 0.03150 0.00748 0.378 BSC 0.248 0.169 -0.020 0° INCHES NOM -0.004 0.035 0.0096 0.382 BSC 0.2519 0.1732 0.026 BSC 0.024 4° MAX 0.47 0.006 0.04 0.012 0.386 BSC 0.256 0.177 -0.029 8° MIN -0.05 0.80 0.19 9.60 BSC 6.30 4.30 -0.50 0° MILLIMETERS NOM -0.10 0.90 0.245 9.70 BSC 6.40 4.40 0.65 BSC 0.60 4° NOTE MAX 1.
PAGE 47
CS4271 11.APPENDIX 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0 60 60 80 80 100 100 120 120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1 Figure 21. DAC Single Speed (fast) Stopband Rejection 0.4 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 22. DAC Single Speed (fast) Transition Band 0.02 0 1 0.015 2 0.01 0.005 4 Amplitude (dB) Amplitude (dB) 3 5 6 0 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.
PAGE 48
CS4271 0.02 0 1 0.015 2 0.01 3 Amplitude (dB) Amplitude (dB) 0.005 4 5 6 0 0.005 7 0.01 8 0.015 9 10 0.45 0.02 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 Figure 27. DAC Single Speed (slow) Transition Band (detail) 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0.05 Figure 28. DAC Single Speed (slow) Passband Ripple 0 60 60 80 80 100 100 120 0 120 0.4 0.
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CS4271 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0 60 60 80 80 100 100 120 120 0.2 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 Figure 33. DAC Double Speed (slow) Stopband Rejection 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 Figure 34. DAC Double Speed (slow) Transition Band 0 0.02 1 0.015 2 0.01 0.005 4 Amplitude (dB) Amplitude (dB) 3 5 6 0 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.
PAGE 50
CS4271 0.2 0 1 0.15 2 0.1 3 Amplitude (dB) Amplitude (dB) 0.05 4 5 6 0 0.05 7 0.1 8 0.15 9 10 0.45 0.2 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 Figure 39. DAC Quad Speed (fast) Transition Band (detail) 0 0.05 0.1 0.15 Frequency(normalized to Fs) 0.2 0.25 Figure 40. DAC Quad Speed (fast) Passband Ripple 0 0 20 40 40 Amplitude (dB) Amplitude (dB) 20 60 60 80 80 100 100 120 120 0.1 0.2 0.3 0.4 0.5 0.6 0.
PAGE 51
0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 Amplitude (dB) Amplitude (dB) CS4271 -60 -70 -80 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -140 0.40 1.0 Frequency (normalized to Fs) 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (normalized to Fs) Figure 45. ADC Single Speed Mode Stopband Rejection Figure 46. ADC Single Speed Mode Transition Band 0.10 0 -1 0.08 -2 0.05 0.
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CS4271 0.10 0 -1 0.08 -2 0.05 -3 0.03 Amplitude (dB) Amplitude (dB) -4 -5 -6 0.00 -0.03 -7 -0.05 -8 -9 -0.08 -10 0.40 0.43 0.45 0.48 0.50 0.53 -0.10 0.00 0.55 Frequency (normalized to Fs) 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (normalized to Fs) Figure 51. ADC Double Speed Mode Transition Band (Detail) Figure 52.
PAGE 53
CS4271 Table 18. Revision History Release A1 PP1 PP2 PP3 F1 Date January 2003 March 2003 October 2003 September 2004 August 2005 Changes Advance Release Preliminary Release - Corrected the description of pins 17 and 18 on page 6. - Corrected the description of pins 17 and 18 on page 8. - Updated Figure 8 on page 23. - Updated Table 9 on page 29. - Updated the DC Electrical Characteristics table on page 17. - Updated the DAC Analog Filter Response tables on pages 10 and 11.