User guide

22 DS686F1
CS4270
Clock-ratio configuration for each mode is outlined in the Table 11 on page 34 and Table 10 on page 33.
In Serial Control Port Mode, the CS4270 defaults to Slave Mode. The user may change this default setting
by changing the status of the FM bits in the Mode Control Register (03h).
5.2.3 System Clocking
The CS4270 operates at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three
speed modes as shown in Table 6.
5.2.4 Clock Ratio Selection
In Serial Control Port Master Mode, the user must configure the mode bits (MCLK_FREQ[2:0]) to set the
speed mode and select the appropriate clock ratios. Changes to these bits should only be done while the
PDN bit is set. Depending on whether the CS4270 is in Master or Slave Mode, different MCLK/LRCK and
SCLK/LRCK ratios may be used. These ratios as well as the Serial Control Port Register Bits are shown
in Table 7, Table 10 on page 33, and Section 8.3 on page 33. ‘0’ = DGND, ‘1’ = VLC.
Mode Sampling Frequency
Single-Speed
4-54 kHz
Double-Speed
50-108 kHz
Quad-Speed
100-216 kHz
Table 6. Speed Modes
Master Mode
Speed Mode MCLK/LRCK SCLK/LRCK LRCK MCLK_FREQ2 MCLK_FREQ1 MCLK_FREQ0
Single-Speed
256 64 Fs 0 0 0
384 64 Fs 0 0 1
512 64 Fs 0 1 0
768 64 Fs 0 1 1
1,024 64 Fs 1 0 0
Double-Speed
128 64 Fs 0 0 0
192 64 Fs 0 0 1
256 64 Fs 0 1 0
384 64 Fs 0 1 1
512 64 Fs 1 0 0
Quad-Speed
64 64 Fs 0 0 0
96 64 Fs 0 0 1
128 64 Fs 0 1 0
192 64 Fs 0 1 1
256 64 Fs 1 0 0
Table 7. Clock Ratios - Serial Control Port Mode