User guide

16 DS686F1
CS4270
Figure 9. Format 0, Left-Justified up to 24-Bit Data
LRCK
SCLK
Channel A - Left
SDATA
+3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4 -5 +3 +2 +1
LSB
+5 +4
MSB
-1 -2 -3 -4
Channel B - Right
Figure 10. Format 1, I²S up to 24-Bit Data
LRCK
SCLK
SDINx
+3 +2 +1+5 +4
-1 -2 -3 -4 -5
+3 +2 +1+5 +4
-1 -2 -3 -4
MSB
MSB
LSB LSB
Channel A - Left Channel B - Right
LRCK
SCLK
SDATA
+5
+4 +3 +2
+1
MSB
-1 -2 -3 -4 -5
32 clocks
Right Channel
LSB
+5
+4 +3 +2
+1
-1 -2 -3 -4
-5
+6
-6
+6
-6
Channel B - Right
LSB MSB LSB
Channel A - Left
Figure 11. Format 2 or 3, Right-Justified 16-Bit or 24-Bit Data (Serial Control Port Mode Only)