Instruction Manual

44 DS657F3
CS4265
6.14 Status Mask - Address 0Eh
Function:
The bits of this register serve as a mask for the Status sources found in the register “Status - Address 0Dh”
on page 43. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status
register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the status
register. The bit positions align with the corresponding bits in the Status register.
6.15 Status Mode MSB - Address 0Fh
6.16 Status Mode LSB - Address 10h
Function:
The two Status Mode registers form a 2-bit code for each Status register function. There are three ways to
update the Status register in accordance with the status condition. In the Rising-Edge Active Mode, the sta-
tus bit becomes active on the arriva l of the c ondition. In the Falling-Ed ge Active Mode, the status bit be-
comes active on the removal of the condition. In Level-Active Mode, the status bit is ac tive during the
condition.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
6.17 Transmitter Control 1 - Address 11h
6.17.1 E to F C-Data Buffer Transfer Inhibit (Bit 6)
Function:
When cleared, C-data E to F buffer transfers are allowed. When set, C-data E to F buffer transfers are
inhibited. See “IEC60958-3 Channel Status (C) Bit Management” on page 53.
6.17.2 C-Data Access Mode (Bit 5)
Function:
When cleared, the C-data buffer will operate in One-byte control port access mode. When set, the C-data
buffer will operate in Two-byte control port access mode. See “IEC60958-3 Channel Status (C) Bit Man-
agement” on page 53.
76543210
Reserved Reserved Reserved EFTCM ClkErrM Reserved ADCOvflM ADCUndrflM
76543210
Reserved Reserved Reserved EFTC1 ClkErr1 Reserved ADCOvfl1 ADCUndrfl1
Reserved Reserved Reserved EFTC0 ClkErr0 Reserved ADCOvfl0 ADCUndrfl0
76543210
Reserved EFTCI CAM Reserved Reserved Reserved Reserved Reserved