User guide
Table Of Contents
- 1. Characteristics and Specifications
- Specified Operating Conditions
- Absolute Maximum Ratings
- Analog Input Characteristics
- A/D Digital Filter Characteristics
- Analog Output Characteristics
- D/A Digital Filter Characteristics
- Switching Characteristics
- Switching Characteristics - Control Port - I²C™ Format
- Switching Characteristics - Control Port - SPI™ Format
- DC Electrical Characteristics
- Digital Interface Characteristics
- 2. Pin Descriptions
- 3. Typical Connection Diagram
- 4. Applications
- 4.1 Overview
- 4.2 Analog Inputs
- 4.3 Analog Outputs
- 4.4 S/PDIF Receiver
- 4.5 Clock Generation
- 4.6 Digital Interfaces
- 4.7 Control Port Description and Timing
- 4.8 Interrupts
- 4.9 Reset and Power-Up
- 4.10 Power Supply, Grounding, and PCB Layout
- 5. Register Quick Reference
- 6. Register Description
- Table 5. DAC De-Emphasis
- Table 6. Receiver De-Emphasis
- Table 7. Digital Interface Formats
- Table 8. ADC One-Line Mode
- Table 9. DAC One-Line Mode
- Table 10. RMCK Divider Settings
- Table 11. OMCK Frequency Settings
- Table 12. Master Clock Source Select
- Table 13. AES Format Detection
- Table 14. Receiver Clock Frequency Detection
- Table 15. Example Digital Volume Settings
- Table 16. ATAPI Decode
- Table 17. Example ADC Input Gain Settings
- Table 18. TXP Output Selection
- Table 19. Receiver Input Selection
- Table 20. Auxiliary Data Width Selection
- 7. Parameter Definitions
- 8. Appendix A: External Filters
- 9. Appendix B: S/PDIF Receiver
- 10. Appendix C: PLL Filter
- 11. Appendix D: External AES3-S/PDIF-IEC60958 Receiver Components
- 12. Appendix E: ADC Filter Plots
- Figure 34. Single-Speed Mode Stopband Rejection
- Figure 35. Single-Speed Mode Transition Band
- Figure 36. Single-Speed Mode Transition Band (Detail)
- Figure 37. Single-Speed Mode Passband Ripple
- Figure 38. Double-Speed Mode Stopband Rejection
- Figure 39. Double-Speed Mode Transition Band
- Figure 40. Double-Speed Mode Transition Band (Detail)
- Figure 41. Double-Speed Mode Passband Ripple
- Figure 42. Quad-Speed Mode Stopband Rejection
- Figure 43. Quad-Speed Mode Transition Band
- Figure 44. Quad-Speed Mode Transition Band (Detail)
- Figure 45. Quad-Speed Mode Passband Ripple
- 13. Appendix F: DAC Filter Plots
- Figure 46. Single-Speed (fast) Stopband Rejection
- Figure 47. Single-Speed (fast) Transition Band
- Figure 48. Single-Speed (fast) Transition Band (detail)
- Figure 49. Single-Speed (fast) Passband Ripple
- Figure 50. Single-Speed (slow) Stopband Rejection
- Figure 51. Single-Speed (slow) Transition Band
- Figure 52. Single-Speed (slow) Transition Band (detail)
- Figure 53. Single-Speed (slow) Passband Ripple
- Figure 54. Double-Speed (fast) Stopband Rejection
- Figure 55. Double-Speed (fast) Transition Band
- Figure 56. Double-Speed (fast) Transition Band (detail)
- Figure 57. Double-Speed (fast) Passband Ripple
- Figure 58. Double-Speed (slow) Stopband Rejection
- Figure 59. Double-Speed (slow) Transition Band
- Figure 60. Double-Speed (slow) Transition Band (detail)
- Figure 61. Double-Speed (slow) Passband Ripple
- Figure 62. Quad-Speed (fast) Stopband Rejection
- Figure 63. Quad-Speed (fast) Transition Band
- Figure 64. Quad-Speed (fast) Transition Band (detail)
- Figure 65. Quad-Speed (fast) Passband Ripple
- Figure 66. Quad-Speed (slow) Stopband Rejection
- Figure 67. Quad-Speed (slow) Transition Band
- Figure 68. Quad-Speed (slow) Transition Band (detail)
- Figure 69. Quad-Speed (slow) Passband Ripple
- 14. Package Dimensions
- 15. Ordering Information
- 16. References
- 17. Revision History
DS583F2 61
CS42516
6.16 ADC Left Channel Gain (address 1Ch)
6.16.1 ADC LEFT CHANNEL GAIN (LGAINX)
Default = 00h
Function:
The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in Table 17.
6.17 ADC Right Channel Gain (address 1Dh)
6.17.1 ADC RIGHT CHANNEL GAIN (RGAINX)
Default = 00h
Function:
The level of the right analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in Table 17.
6.18 Receiver Mode Control (address 1Eh)
6.18.1 SERIAL PORT SYNCHRONIZATION (SP_SYNC)
Default = 0
0 - CX & SAI Serial Port timings not in phase
1 - CX & SAI Serial Port timings are in phase
Function:
Forces the LRCK and SCLK from the CX & SAI Serial Ports to align and operate in phase. This func-
tion will operate when both ports are running at the same sample rate or when operating at different
sample rates.
76543210
Reserved Reserved LGAIN5 LGAIN4 LGAIN3 LGAIN2 LGAIN1 LGAIN0
76543210
Reserved Reserved RGAIN5 RGAIN4 RGAIN3 RGAIN2 RGAIN1 RGAIN0
Binary Code Decimal Value Volume Setting
001111 +15 +15 dB
001010 +10 +10 dB
000101 +5 +5 dB
000000 0 0 dB
111011 -5 -5 dB
110110 -10 -10 dB
110001 -15 -15 dB
Table 17. Example ADC Input Gain Settings
76543210
SP_SYNC Reserved DE-EMPH1 DE-EMPH0 INT1 INT0 HOLD1 HOLD0