User guide
Table Of Contents
- 1. Characteristics and Specifications
- Specified Operating Conditions
- Absolute Maximum Ratings
- Analog Input Characteristics
- A/D Digital Filter Characteristics
- Analog Output Characteristics
- D/A Digital Filter Characteristics
- Switching Characteristics
- Switching Characteristics - Control Port - I²C™ Format
- Switching Characteristics - Control Port - SPI™ Format
- DC Electrical Characteristics
- Digital Interface Characteristics
- 2. Pin Descriptions
- 3. Typical Connection Diagram
- 4. Applications
- 4.1 Overview
- 4.2 Analog Inputs
- 4.3 Analog Outputs
- 4.4 S/PDIF Receiver
- 4.5 Clock Generation
- 4.6 Digital Interfaces
- 4.7 Control Port Description and Timing
- 4.8 Interrupts
- 4.9 Reset and Power-Up
- 4.10 Power Supply, Grounding, and PCB Layout
- 5. Register Quick Reference
- 6. Register Description
- Table 5. DAC De-Emphasis
- Table 6. Receiver De-Emphasis
- Table 7. Digital Interface Formats
- Table 8. ADC One-Line Mode
- Table 9. DAC One-Line Mode
- Table 10. RMCK Divider Settings
- Table 11. OMCK Frequency Settings
- Table 12. Master Clock Source Select
- Table 13. AES Format Detection
- Table 14. Receiver Clock Frequency Detection
- Table 15. Example Digital Volume Settings
- Table 16. ATAPI Decode
- Table 17. Example ADC Input Gain Settings
- Table 18. TXP Output Selection
- Table 19. Receiver Input Selection
- Table 20. Auxiliary Data Width Selection
- 7. Parameter Definitions
- 8. Appendix A: External Filters
- 9. Appendix B: S/PDIF Receiver
- 10. Appendix C: PLL Filter
- 11. Appendix D: External AES3-S/PDIF-IEC60958 Receiver Components
- 12. Appendix E: ADC Filter Plots
- Figure 34. Single-Speed Mode Stopband Rejection
- Figure 35. Single-Speed Mode Transition Band
- Figure 36. Single-Speed Mode Transition Band (Detail)
- Figure 37. Single-Speed Mode Passband Ripple
- Figure 38. Double-Speed Mode Stopband Rejection
- Figure 39. Double-Speed Mode Transition Band
- Figure 40. Double-Speed Mode Transition Band (Detail)
- Figure 41. Double-Speed Mode Passband Ripple
- Figure 42. Quad-Speed Mode Stopband Rejection
- Figure 43. Quad-Speed Mode Transition Band
- Figure 44. Quad-Speed Mode Transition Band (Detail)
- Figure 45. Quad-Speed Mode Passband Ripple
- 13. Appendix F: DAC Filter Plots
- Figure 46. Single-Speed (fast) Stopband Rejection
- Figure 47. Single-Speed (fast) Transition Band
- Figure 48. Single-Speed (fast) Transition Band (detail)
- Figure 49. Single-Speed (fast) Passband Ripple
- Figure 50. Single-Speed (slow) Stopband Rejection
- Figure 51. Single-Speed (slow) Transition Band
- Figure 52. Single-Speed (slow) Transition Band (detail)
- Figure 53. Single-Speed (slow) Passband Ripple
- Figure 54. Double-Speed (fast) Stopband Rejection
- Figure 55. Double-Speed (fast) Transition Band
- Figure 56. Double-Speed (fast) Transition Band (detail)
- Figure 57. Double-Speed (fast) Passband Ripple
- Figure 58. Double-Speed (slow) Stopband Rejection
- Figure 59. Double-Speed (slow) Transition Band
- Figure 60. Double-Speed (slow) Transition Band (detail)
- Figure 61. Double-Speed (slow) Passband Ripple
- Figure 62. Quad-Speed (fast) Stopband Rejection
- Figure 63. Quad-Speed (fast) Transition Band
- Figure 64. Quad-Speed (fast) Transition Band (detail)
- Figure 65. Quad-Speed (fast) Passband Ripple
- Figure 66. Quad-Speed (slow) Stopband Rejection
- Figure 67. Quad-Speed (slow) Transition Band
- Figure 68. Quad-Speed (slow) Transition Band (detail)
- Figure 69. Quad-Speed (slow) Passband Ripple
- 14. Package Dimensions
- 15. Ordering Information
- 16. References
- 17. Revision History

DS583F2 49
CS42516
6.5 Interface Formats (address 04h)
6.5.1 DIGITAL INTERFACE FORMAT (DIFX)
Default = 01
Function:
These bits select the digital interface format used for the CODEC Serial Port and Serial Audio Interface
Port when not in One-Line Mode. The required relationship between the Left/Right clock, serial clock,
and serial data is defined by the Digital Interface Format and the options are detailed in 11-12.
6.5.2 ADC ONE_LINE MODE (ADC_OLX)
Default = 00
Function:
These bits select which mode the ADC will use. By default, One-Line Mode is disabled, but it can be
selected using these bits. Please see Figures 13 and 14 to see the format of One-Line Mode 1 and
One-Line Mode 2.
6.5.3 DAC ONE_LINE MODE (DAC_OLX)
Default = 00
Function:
These bits select which mode the DAC will use. By default, One-Line Mode is disabled, but it can be
selected using these bits. Please see Figures 13 and 14 to see the format of One-Line Mode 1 and
One-Line Mode 2.
76543210
DIF1 DIF0 ADC_OL1 ADC_OL0 DAC_OL1 DAC_OL0 SAI_RJ16 CODEC_RJ16
DIF1 DIF0 Description Format Figure
00
Left-Justified, up to 24-bit data
0 11
01
I²S, up to 24-bit data
1
10
10
Right-Justified, 16-bit or 24-bit data
2 12
11
Reserved
--
Table 7. Digital Interface Formats
ADC_OL1 ADC_OL0 Description Format Figure
00
DIF: take the DIF setting from reg04h[7:6]
--
01
One-Line #1
3
13
10
One-Line #2
4
14
11
Reserved
--
Table 8. ADC One-Line Mode
DAC_OL1 DAC_OL0 Description Format Figure
00
DIF: take the DIF setting from reg04h[7:6]
--
01
One-Line #1
3
13
10
One-Line #2
4
14
11
Reserved
--
Table 9. DAC One-Line Mode