User guide

24 DS583F2
CS42516
4.5 Clock Generation
The clock generation for the CS42516 is shown in the figure below. The internal MCLK is derived from the
output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the SW_C-
TRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL lock
to the other source input.
4.5.1 PLL and Jitter Attenuation
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming S/PDIF data stream.
There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is im-
portant. For this reason, the PLL has been designed to have good jitter attenuation characteristics as
shown in Figure 28 on page 79.
The PLL can be configured to lock onto the incoming SAI_LRCK signal from the Serial Audio Interface
Port and generate the required internal master clock frequency. By setting the PLL_LRCK bit to a ‘1’ in
the register “Clock Control (address 06h)” on page 52, the PLL will lock to the incoming SAI_LRCK and
generate an output master clock (RMCK) of 256Fs. Table 2 shows the output of the PLL with typical input
Fs values for SAI_LRCK.
See “Appendix C: PLL Filter” on page 77 for more information concerning PLL operation, required filter
components, optimal layout guidelines, and jitter-attenuation characteristics.
SAI_LRCK
(slave mode)
Recovered
S/PDIF Clock
0
1
PLL (256Fs)
8.192 -
49.152 MHz
00
01
PLL_LRCK bit
SW_CTRLx bits
(manual or auto
switch)
OMCK
Auto Detect
Input Clock
1,1.5, 2, 4
single
speed
256
double
speed
128
quad
speed
64
single
speed
4
double
speed
2
quad
speed
1
00
01
10
00
01
10
00
01
10
00
01
10
not OLM
OLM #1
CODEC_FMx bits
SAI_FMx bits
DAC_OLx
or ADC_OLx bits
ADC_OLx and
ADC_SP SELx bits
SAI_SCLK
CX_SCLK
CX_LRCK
SAI_LRCK
RMCK
OLM #2
not OLM
OLM #1
OLM #2
128FS
256FS
128FS
256FS
Internal
MCLK
00
01
10
11
RMCK_DIVx bits
2
4
X2
Figure 9. CS42516 Clock Generation