User guide

DS583F2 13
CS42516
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI
™
FORMAT
(T
A
= -10 to +70° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic
1=VLC, C
L
=30pF)
Notes:
20. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum
allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should
be safe for all possible conditions.
21. Data must be held for sufficient time to bridge the transition time of CCLK.
22. For f
sck
<1 MHz.
Parameter Symbol Min Typ Max Units
CCLK Clock Frequency (Note 20)
f
sck
0-6.0MHz
CS
High Time Between Transmissions
t
csh
1.0 - - s
CS
Falling to CCLK Edge
t
css
20 - - ns
CCLK Low Time
t
scl
66 - - ns
CCLK High Time
t
sch
66 - - ns
CDIN to CCLK Rising Setup Time
t
dsu
40 - - ns
CCLK Rising to DATA Hold Time (Note 21)
t
dh
15 - - ns
CCLK Falling to CDOUT Stable
t
pd
--50ns
Rise Time of CDOUT
t
r1
--25ns
Fall Time of CDOUT
t
f1
--25ns
Rise Time of CCLK and CDIN (Note 22)
t
r2
--100ns
Fall Time of CCLK and CDIN (Note 22)
t
f2
--100ns
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
pd
CDOUT
t
csh
Figure 4. Control Port Timing - SPI Format