User Manual

46 DS656F3
CS4245
6.5.2 Master Clock 2 Frequency (Bits 2:0)
Function:
These bits set the frequency of the supplied MCLK2 signal. See Table 13 for the appropriate settings.
6.6 Signal Selection - Address 06h
6.6.1 Auxiliary Output Source Select (Bits 6:5)
Function:
These bits are used to select the analog output source. Please refer to Table 14.
6.6.2 Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC are enabled. Please refer to
“Internal Digital Loopback” on page 36.
6.6.3 Asynchronous Mode (Bit 0)
Function:
When this bit is set, the DAC and ADC may be operated at independent asynchronous sample rates de-
rived from MCLK1 and MCLK2. When this bit is cleared, the DAC and ADC must operate at synchronous
sample rates derived from MCLK1.
MCLK2 Divider MCLK2 Freq2 MCLK2 Freq1 MCLK2 Freq0
÷1 000
÷1.5 001
÷2 010
÷3 011
÷4 100
Reserved 101
Reserved 11x
Table 13. MCLK 2 Frequency
76543210
Reserved AOutSel1 AOutSel0 Reserved Reserved Reserved LOOP ASynch
AOutSel1 AOutSel0 Auxiliary Output Source
0 0 High Impedance
0 1 DAC Output
1 0 PGA Output
11 Reserved
Table 14. Auxiliary Output Source Selection