User Manual

DS656F3 45
CS4245
6.4.2 ADC Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK1, SCLK1 and SDOUT is defined by the ADC Digital Interface
Format bit. The options are detailed in Table 11 and may be seen in Figure 7 and Figure 8.
6.4.3 Mute ADC (Bit 2)
Function:
When this bit is set, the serial audio output of the both ADC channels is muted.
6.4.4 ADC High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled. The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See “High-Pass Filter and DC Offset Calibration” on
page 32.
6.4.5 ADC Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for serial audio port 1. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
6.5 MCLK Frequency - Address 05h
6.5.1 Master Clock 1 Frequency (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK1 signal. See Table 12 for the appropriate settings.
ADC_DIF Description Format Figure
0 Left-Justified, up to 24-bit data (default) 0 7
1 I²S, up to 24-bit data 1 8
Table 11. ADC Digital Interface Formats
76543210
Reserved
MCLK1
Freq2
MCLK1
Freq1
MCLK1
Freq0
Reserved
MCLK2
Freq2
MCLK2
Freq1
MCLK2
Freq0
MCLK1 Divider MCLK1 Freq2 MCLK1 Freq1 MCLK1 Freq0
÷1 000
÷1.5 001
÷2 010
÷3 011
÷4 100
Reserved 101
Reserved 11x
Table 12. MCLK 1 Frequency