Manual

28 DS603F2
CS42418
Left Channel
Right Channel
DAC_SDINx
ADC_SDOUT
+3 +2 +1+5 +4
-1
-2 -3 -4 -5
+3 +2 +1+5 +4
-1
-2 -3 -4
MSB
MSB
LSB LSB
DAC_LRCK
ADC_LRCK
DAC_SCLK
ADC_SCLK
Figure 12. I²S Serial Audio Formats
I²S Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
Master Slave
16
64 Fs 48, 64, 128 Fs Single-Speed Mode
64 Fs 64 Fs Double-Speed Mode
64 Fs 64 Fs Quad-Speed Mode
18 to 24
64, 128, 256 Fs 48, 64, 128 Fs Single-Speed Mode
64 Fs 64 Fs Double-Speed Mode
64 Fs 64 Fs Quad-Speed Mode
DAC_LRCK
ADC_LRCK
DAC_SCLK
ADC_SCLK
Left Channel
Right Channel
DAC_SDINx
ADC_SDOUT
+3 +2 +1+5 +4
-1 -2 -3 -4 -5
+3 +2 +1+5 +4
-1
-2 -3 -4
MSB LSB MSB LSB
Figure 13. Left-Justified Serial Audio Formats
Left-Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
Master Slave
16
64 Fs 32, 48, 64, 128 Fs Single-Speed Mode
64 Fs 32, 64 Fs Double-Speed Mode
64 Fs 32, 64 Fs Quad-Speed Mode
18 to 24
64, 128, 256 Fs 48, 64, 128 Fs Single-Speed Mode
64 Fs 64 Fs Double-Speed Mode
64 Fs 64 Fs Quad-Speed Mode