User Manual

DS899F1 34
CS4234
SDIN1 SDIN2
MCL K = 12.288/24.576MHz
FS/LRCK = 48/96kHz
SCLK = 12.288/24.576MHz
Slot 1 [31:0] Slot 2 [31:0] Slot 3 [31:0] Slot 4 [31:0] Slot 5 [31:0] Slot 6 [31:0] Slot 7 [31:0] Slot 8 [31:0] Slot 1 [31:0] Slot 2 [31:0] Slot 3 [31:0] Slot 4 [31:0] Slot 5 [31:0] Slot 6 [31:0] Slot 7 [31:0] Slot 8 [31:0]
SDIN1 SDIN2
MCLK = 24. 576MH z
FS/LRCK = 48kHz
SCLK = 24 .576 MH z
…→……→……→…
Slot 8 [31 :0] Slot 9 [31:0] Slot 8 [31 :0] Slot 9 [31:0]
Slot 1 [31:0] Slot 1 [31:0]
Slot 4 [31:0] Slot 5 [31:0] Slot 4 [31:0] Slot 5 [31:0]
…→…
Slot 16 [31:0] Slot 16 [31:0]
Slot 12 [31:0] Slot 13 [31:0] Slot 12 [31:0] Slot 13 [31:0]
001 Slots 5-8 of SDIN1
010
Slots 9-12 of SDIN1
LL Source [2:0] Low Latency Data is in:
000 Slots 1-4 of SDIN1
101
Slots 5-8 of SDIN2
DAC1-4 Source [2:0]
000 001
DAC1-4 Data is in:
Slots 1-4 of SDIN1 Slots 5-8 of SDIN1
Slots 9-12 of SDIN1
Slots 13-16 of SDIN1
111
Slots 13-16 of SDIN1
100
011 100
Slots 1-4 of SDIN2
011
110
Slots 1-4 of SDIN2
010
Coded into the LSBs of Slots 5-7 of SDIN1
Coded into the LSBs of Slots 9-11 of SDIN1
DAC5 Source [2:0]
000 Coded into the LSBs of Slots 1-3 of SDIN1
010
Reserved
DAC5 Data is in:
011 100
Coded into the LSBs of Slots 13-15 of SDIN1
Determined by the Masking bits
001
110
Slots 9-12 of SDIN2
101 110
Reserved Reserved
101
Slots 5-8 of SDIN2
111 Slots 13-16 of SDIN2111
Slots 9-12 of SDIN2
Slots 13-16 of SDIN2
Figure 21. DAC1-4, Low Latency, and DAC5 Path Serial Data Source Selection