User Manual

CS4228A

5.9 Serial Port Mode

Address 0x0D

DCK1:0 Sets the number of Serial Clocks (SCLK) per Fs period (LRCLK)

DMS1:0 Sets the master/slave mode of the serial audio port

*0 - Slave (External LRCLK, SCLK)

1- Reserved

2- Reserved

3- Master(No48FsSCLKinBRM)

DDF2:0 Serial Port Data Format

0 - Right Justified, 24-bit

1 - Right Justified, 20-bit

2 - Right Justified, 16-bit

3 - Left Justified, maximum 24-bit

*4 - I

S compatible, maximum 24-bit

5 - One-line Data Mode, available in BRM only

6- Reserved

7- Reserved

5.10 Chip Status

Address 0x0E

CLKERR Clocking system status, read only

0- NoError

1 - No MCLK is present, or a request for clock change is in progress

ADCOVL ADC overflow bit, read only

0 - No overflow

1- ADCoverflowhasoccurred

76543210

DCK1 DCK0 DMS1 DMS0 RESERVED DDF2 DDF1 DFF0

10000100

DCK1:0 BRM (Fs) HRM (Fs)

032(1)(3)

148(2)(3)

2 *64 32 (1)

3 128 64

Notes: 1. All formats will default to 16 bits

2. Slave mode only

3. Invalid mode

7 6543210

CLKERR ADCOVL RESERVED

XX000000