User Manual

CS4202
36 DS549PP2
4.21 GPIO Pin Wakeup Mask Register (Index 52h)
GW[4:0] GPIO Pin Wakeup. This register provides a mask for determining if an input GPIO change will
generate a wakeup even t (0 = no, 1 = yes). When the AC-link is powered up, a wa keup event
will be communicated through the assertion of GPIO_INT = 1 in input Slot 12. When the
AC-link is powered do wn (Powerdown Control/Status Register (Index 26h) bi t PR4 = 1 for pri-
mary codecs), a wakeup event will be communicated through a ‘0’ to ‘1’ transition on
SDATA_IN.
Default 0000h
GPIO bits which have been programmed as inputs, “sticky”, and “wakeup”, upon transition either (high-to-low) or
(low-to-high) depending on pin polarity, will cause an AC-link wakeup if and only if the AC-link was powered down.
Once the controller has re-established communication with the CS4202 following a Warm Reset, it will continue to
signal the wakeup event through the GPIO_INT bit of input Slot 12 until the AC ’97 controller clears the inter-
rupt-causing bit in the GPIO Pin Status Reg ister (Index 54 h); or the “wakeup”, config, or “sticky” status of that GPIO
pin changes.
After a Cold Reset or a modem Register Reset (see Extended Modem ID Register (Index 3Ch)) this register defaults
to all 0’s, specifying no wakeup event. The upper 11 bits of this register always return ‘0’.
4.22 GPIO Pin Status Register (Index 54h)
GI[4:0] GP IO Pin Status. This regis ter reflec ts th e state of all GPIO pin inputs and outputs. These
values are also reflected in Slot 12 of every SDATA_IN frame. GPIO inputs configured as
“sticky” are ‘clear ed ’ by w riting a ‘0’ to the co rr es po nd in g bit of this re gis ter . Th e GP IO_INT
bit in input Slot 12 is ‘cleared’ by clearing all interrupt-causing bits in this register.
Default 0000h
GPIO pins which have been progra mmed as inputs and “ sticky”, upon transition either (h igh-to-low) or (low-to-hig h)
depending on pin polarity, will cause the individual GI bit to be ‘set’, and remain ‘set’ until ‘cleared’. GPIO pins which
have been programmed a s o utputs are controlled either through output Slot 12 or through this registe r, depending
on the state of the GPOC bit in the Misc. Crystal Control Register (Index 60h). If the GPOC bit is ‘cleared’, the GI
bits in this register are read-only and reflect the status of the corresponding GPIO output pin ‘set’ through output
slot 12. If the GPOC bit is ‘set’, the GI bits in this register are read/write bits and control the corresponding GPIO
output pins.
The default value is always the state of the GPIO pin. The upper 11 bits of this register should be forced to zero in
this register and input Slot 12.
4.23 AC Mode Control Register (Index 5Eh)
ASPM Analog S/PDIF Mode. The ASPM bit controls the input source to the S/PDIF transmitter block.
When ‘clear’, the S/PDIF transmitter will receive data from the corresponding AC-link output
slots. The actual slots are determined by the state of the SPSA[1:0] bits in the Extended Audio
Status/Control Register (Index 2Ah). If ‘set’, the S/PDIF transmitter block will receive data
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
00000000000GW4GW3GW2GW1GW0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
00000000000GI4GI3GI2GI1GI0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0000ASPM0TMMDDM00ASA1 ASA0 0 0 0 0