CS35L32 Boosted Class D Amplifier with Speaker-Protection Monitoring and Flash LED Drivers Mono Class D Speaker Amplifier Flash LED Drivers • Two-level Class G operation: • Boosted: 5 V nominal • Bypassed: battery voltage is supplied directly • 2.5-mA quiescent current, monitors powered down • 1.
CS35L32 • Error status bit, including the following: • Stopped MCLK error • Protection: • Low battery detection with programmable thresholds • Latched overtemperature shutdown • VP UVLO error • Latched amplifier output short circuit shutdown • Overtemperature warning • LED short or open detection and LED driver shutdown • Overtemperature error • Flash inhibit LED current reduction • Boost converter overvoltage error • Low battery flash LED current reduction • Boost inductor current-limiting error • VP under
CS35L32 The battery voltage, speaker voltage, and speaker current signals are monitored, digitized using converters, and serialized over an I2S bus. The speaker monitoring signals are part of a speaker-protection algorithm that is managed externally to the CS35L32. Outgoing data is sent over I2S with the CS35L32 in Slave or Master Mode. Battery voltage monitor data is accessible through I2C. An integrated dual LED driver operates up to two LEDs in Flash Mode or Movie Mode.
CS35L32 Table of Contents 1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Register Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2 Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3 Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . 8 7.1 Device ID A and B . . . . . . . . . .
CS35L32 1 Pin Descriptions 1 Pin Descriptions ‘ A1 ‘ A2 SDA A3 SCL ‘ ‘ ‘ ‘ A5 A4 SDOUT ‘ SCLK ‘ A6 MCLK FLOUT2/ AD0 ‘ ‘ B1 B2 B3 B4 B5 B6 VP INT RESET LRCK GNDPLED FLOUT1 ‘ ‘ ‘ ‘ ‘ C1 C2 C3 C4 C5 C6 SW GNDP GNDP FLINH GNDA VA ‘ D1 SW ‘ ‘ D2 D3 SPKOUT+ SPKOUT–/ VSENSE– ‘ ‘ ‘ D4 ‘ D5 FLEN ‘ D6 IREF+ FILT+ ‘ ‘ E1 E2 E3 E4 E5 E6 VBST SPKRSUPPLY IN– IN+ ISENSE–/ VSENSE+ ISENSE+ LED Digital I/O Audio Power Supply General Ground
CS35L32 1 Pin Descriptions Table 1-1. Pin Descriptions (Cont.) Ball Name RESET Ball Power Internal I/O Ball Description Number Supply Connection — B3 VA I Reset. When asserted, the device enters a low-power mode, outputs are set to Hi-Z, and I²C register values are set to defaults. Outputs are Hi-Z except those with weak pull-ups or pull-downs as mentioned. Driver — State at Reset Hysteresis Low on CMOS input Receiver LED FLEN D4 FLINH C4 FLOUT1 B6 FLOUT2/AD0 A6 VA I Flash Enable.
CS35L32 2 Typical Connection Diagram 2 Typical Connection Diagram 1 H Battery 3.0–5.25 V 10 F PMU * LBST 0.1 F VP SW CS35L32 VA 1.71–1.89 V SPKRSUPPLY VA 0.1 F * FILT+ 4.7 F * Note 2 Note 1 VBST 0.1 F GNDA * CBST 10 F 10 F * GNDP RP RP RP_I * IN+ * IN– Line Input 1 Note 3 FLOUT1 SDA See Note 7 for LED and I2C addressing options. FLOUT2 / AD0 SCL GNDPLED INT Applications Processor RESET IREF+ RBST_SNS 44.
CS35L32 3 Characteristics and Specifications 3 Characteristics and Specifications Table 3-1. Recommended Operating Conditions GNDA = GNDP = 0 V, all voltages with respect to ground. Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability.
CS35L32 3 Characteristics and Specifications Table 3-4. Boost Converter Characteristics Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, amp gain = 12 dB, GNDA = GNDP = 0 V, TA = +25°C, MCLKINT = 6 MHz. MCLKINT is explained in Section 4.13.1 and Section 7.7. Parameters Boost output voltage Symbol VBST Boost output voltage tolerance Load regulation Line regulation Boost FET peak-current limit (See Section 7.10.
CS35L32 3 Characteristics and Specifications Table 3-6. Speaker Amplifier Output Characteristics Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, 1-kHz input, amp gain = 12 dB, GNDA = GNDP = 0 V, TA = +25°C, measurement bandwidth is 20 Hz to 20 kHz, Fs = 48 kHz, MCLKINT = 6 MHz. MCLKINT is explained in Section 4.13.1 and Section 7.7.
CS35L32 3 Characteristics and Specifications Table 3-7. Signal Monitoring Characteristics Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, amp gain = 12 dB, 0.1- sense resistor, GNDA = GNDP = 0 V, TA = +25°C. Measurement bandwidth is 20 Hz to 20 kHz, Fs = 48 kHz, Input Signal = 1 kHz, MCLKINT = 6 MHz, MCLKINT is explained in Section 4.13.1 and Section 7.7.
CS35L32 3 Characteristics and Specifications Table 3-9. PSRR Characteristics Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = VP, amp gain = 12 dB, GNDA = GNDP = 0 V, TA = +25°C.
CS35L32 3 Characteristics and Specifications Table 3-12. Switching Specifications: ADSP in I2S Mode Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, TA = +25°C, Inputs: Logic 0 = GNDA = GNDP = 0 V, Logic 1 = VA; CLOAD = 30 pF. Section 9 describes some parameters in detail; input timings are measured at VIL and VIH thresholds; output timings are measured at VOL and VOH thresholds (see Table 3-8).
CS35L32 3 Characteristics and Specifications Table 3-13. Switching Specifications: I²C Control Port Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, TA = +25°C, Inputs: Logic 0 = GNDA = GNDP = 0 V, Logic 1 = VA; SDA load capacitance equal to maximum value of CB specified below; minimum SDA pull-up resistance, RP(min).1 Section 9 describes some parameters in detail.
CS35L32 4 Functional Description 4 Functional Description See Section 4.6 “Boost Converter.” VP VBST VA SW ADC Low Battery ManagementSee Section 4.4. I 2C Class G Override Class G Class D Power Stage SPKR SUPPLY Class D Front End VREF IN+ IN– FLOUT1 FLOUT2/AD0 GNDPLED Control, Sensing, and Fault Protection Current Mode Synchronous Boost Controller Soft Ramp VCOM FILT+ FLEN FLINH Current Sense Bandgap Voltage Generation VREF Generation See Section 4.9 “LED Driver.
CS35L32 4.3 Speaker Amplifier To clear any status bits set due to the initiation of a path or block, all interrupt status bits should be read after reset and before normal operation begins. Otherwise, unmasking these previously set status bits causes INT to assert. Table 4-1. Interrupt Status Registers and Corresponding Mask Registers Status Registers Mask Registers Interrupt Status 1 (Audio) (Section 7.19) Interrupt Mask 1 (Section 7.16) Interrupt Status 2 (Monitors) (Section 7.
CS35L32 4.4 Low-Battery Management 4.3.2 Class G Operation with LEDs On If LEDs are active, the speaker amplifier supply in one of the following supply modes, as specified by VBOOST_MNG (see Section 4.10.3 and Section 7.12 for details): • Class G operation defaults to the higher supply setting: that requested by the LEDs or that requested by Class G. The latter takes into account both thresholds VIN1THOF and VIN1THON, as described in Section 4.3.1.
CS35L32 4.5 Undervoltage Lockout (UVLO) 4.5 Undervoltage Lockout (UVLO) If the VP level falls below the lockout threshold specified in Table 3-3, UVLO protection shuts down all analog circuitry of the CS35L32. Autorecovery occurs as VP rises above the lockout threshold by a voltage equal to the specified hysteresis. During a UVLO condition, control port, UVLO detection, serial clock, watchdog, and thermal detection circuitry stay active.
CS35L32 4.8 Signal Monitoring 4.7.1 Error Conditions Table 4-3 lists overtemperature error status and mask bits. Table 4-3. Die Temperature Monitoring Configuration Error Overtemperature error/Overtemperature error mask Overtemperature warning/Overtemperature warning mask Overtemperature error release Cross-Reference to Register Field Description OTE p. 41/M_OTE p. 40 OTW p. 41/M_OTW p. 40 OTE_RLS p.
CS35L32 4.8 Signal Monitoring 4.8.2 Monitoring Voltage across the Load—VMON As shown in Fig. 4-5, monitoring on VMON is accomplished via the VSENSE± pins. Table 3-7 gives operating and performance specifications for this ADC path. The following equation determines the VMON voltage (in Volts): D OUT 6.25 VA VMON = ------------------- -------------------------- 1.
CS35L32 4.9 LED Driver 4.8.4 Monitoring Voltage on the VP Pin—VPMON Monitoring of the voltage present on the VP pin is integrated internally to the CS35L32. The operating specifications for this ADC path are given in Table 3-7. To determine the voltage present on VP, the following equation must be used: D + 128 OUT 1 VP = --------------------------------------- 5 + -------- VA 255 1.8 DOUT is the digital output word (see VPMON, p.
CS35L32 4.9 LED Driver The CS35L32 is driven to flash when FLEN is asserted high. The I2C interface allows a host to program Flash and Movie Mode currents, as well as a flash timer. The corresponding registers for these settings are LED_FLCUR (see p. 43), LED_ MVCUR (see p. 44), and TIMER (see p. 44). The flash event terminates at the end of a period determined by the flash timer and optionally when FLEN is deasserted; this option is configured through TIMEOUT_MODE (see p. 44).
CS35L32 4.10 Power Budgeting 4.9.3 LED Lighting Status Register The LED lighting status register (see Section 7.22) reports the state of LEDs and their controls. Status is reported for LED1 and LED2 flash events, indicating whether each LED is driven with current set by the flash setting. Likewise, status is reported for LED1 and LED2 Movie Mode events, indicating whether each LED is driven with current set by the Movie Mode setting.
CS35L32 4.11 Audio/Data Serial Port (ADSP) 4.10.3 Audio and LED Operation When audio and LEDs are operating simultaneously, the user can select one the following courses of action: • By clearing AUDIOGAIN_MNG, if the CS35L32 enters load management mode due to the conditions listed in Section 4.10, audio gain is reduced once by 3 dB (no reduction for 9-dB gain). If the condition persists, the CS35L32 examines ILED_MNG and responds according to Section 4.10.2.
CS35L32 4.11 Audio/Data Serial Port (ADSP) Table 4-6. ADSP Operational Mode and Pin Configurations M/S SDOUT_3ST ADSP Operational Mode SDOUT Pin Driver LRCK Pin Driver SCLK Pin Driver 0 0 I2S Slave Mode Output Input Input 0 1 I2S Slave Mode Hi-Z Input Input 1 0 I2S Master Mode Output Output Output 1 1 I2S Master Mode Hi-Z Output Output 4.11.1.
CS35L32 4.12 Signaling Format The CS35L32 transmits data that is from 24 to 32 bits deep per channel sample. If fewer than 24 serial clocks are present per channel frame (half LR clock period), it outputs as many bits as there are clocks. If there are more than 24 serial clocks per channel frame, it outputs the bits shown in the extended section for the additional clock cycles after the 24th bit. Any bit beyond the 24th, if marked as reserved, is zero.
CS35L32 4.12 Signaling Format Table 4-8. SDOUT Monitor Data Description (Cont.) Function Signal Monitoring, Section 4.8. LED Driver Section 4.9. Power down Data Descriptor VMON_OVFL (VMON overflow) IMON_OVFL (IMON overflow) VPMON_OVFL (VPMON overflow) VMON (voltage monitor) IMON (current monitor) VPMON (battery voltage) LED12_FLEV (LED12 flash event) Description xMON overflow.
CS35L32 4.12 Signaling Format 4.12.3 Transmitting Data from a Dual-CS35L32 Configuration To indicate a dual-CS35L32 configuration where the SDOUT line is shared, the user must set SHARE (see p. 39). When two CS35L32 devices are available on the same board, each device is identified by its I2C address. The AD0 pin is shared by FLOUT2. Upon power-up or upon deasserting RESET, each CS35L32 reads the AD0 pin logic level and configures its chip address. Transmission starts when SDOUT_3ST (see p.
CS35L32 4.13 Device Clocking Table 4-13.
CS35L32 4.14 Control Port Operation 4.13.3 Error Conditions MCLK, SCLK, and LRCK are monitored for clocking and configuration errors. If an MCLK or ADSP error occurs, the respective MCLK_ERR or ADSPCLK_ERR bit is set, and, if the respective mask bit is cleared, INT is asserted. • MCLK error (MCLK_ERR). If MCLK were to stop abruptly while the boost converter or amplifier’s output stages are switching, it could damage or destroy the device.
CS35L32 4.14 Control Port Operation 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 x 24 25 26 27 28 19 SCL CHIP ADDRESS (WRITE) 0 0 0 0 x AD0 Slave Address START SDA Source MAP BYTE 0 ACK Pullup x x x x x 7 6 1 7 0 Data to Addr X ACK DATA DATA DATA x MAP Addr INCR = 1 SDA 0 R/W = 0 1 ACK 6 1 0 7 6 1 0 Data to Addr X+1 Data to Addr X+n Master Master ACK STOP Master Master Master Master Slave Slave Slave Slave Slave Pullup Figure 4-11.
CS35L32 5 Applications Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 10000001 (chip address and read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Note: For I2C reads, the interrupt status registers and the register at the address that precedes an interrupt status register must be read individually and not as a part of an autoincremented control-port read.
CS35L32 5.3 External Component and PCB Design Considerations—EMI Output To avoid the current transient on the VP node, the boost converter management must be configured for a fixed 5-V boost operation (VBOOST_MNG = 11) before issuing a flash event. VBOOST_MNG may be reconfigured to the desired management mode after a flash event. The following sequence should be followed when issuing a flash event: • Configure VBOOST_MNG to fixed 5-V Mode (VBOOST_MNG = 11). • Trigger a flash event by asserting FLEN.
CS35L32 5.5 Inductor Selection Ball A1 Location Indicator Figure 5-2. Ground Ball Locations (Shown in Gray) Also, as space permits, traces should be wider than 12 mils as soon as they clear the balls of the device. The traces should remain wide for at least 300 mils after they leave the device. 5.5 Inductor Selection Table 5-1, “Recommended Inductors,” lists the inductors recommended for use with the CS35L32. Table 5-1.
CS35L32 6 Register Quick Reference 6 Register Quick Reference Default values are shown below the bit names. Adr. 0x01 p. 36 0x02 p. 36 0x03 p. 36 0x04 0x05 p. 36 0x06 p.
CS35L32 7 Register Descriptions 7 Register Descriptions All registers are read/write except for the chip ID and revision register and the status registers, which are read only. The user must not change reserved registers from their default state. 7.1 Device ID A and B R/O 7 6 Address 0x01 5 4 3 2 DEVIDA[3:0] Default 0 0 1 0 0 1 DEVIDB[3:0] 1 1 0 1 7.2 Device ID C and D R/O 7 6 Address 0x02 5 4 3 2 DEVIDC[3:0] Default 1 0 1 0 1 1 DEVIDD[3:0] 1 0 0 0 7.
CS35L32 7.6 Power Control 2 7.6 Power Control 2 R/W Address 0x07 7 6 5 4 3 PDN_VMON PDN_IMON PDN_VPMON — SDOUT_3ST 1 1 1 0 1 Default 2 1 0 — 0 0 0 Bits Name Description 7 PDN_ VMON Power-down VMON ADC. Configures the power state of the ADC front end and the ADC used to monitor the VSENSE± input pins to create the VMON data. 0 Powered up 1 (Default) Powered down 6 PDN_ IMON Power-down IMON ADC.
CS35L32 7.9 Battery Voltage Monitor 7.9 Battery Voltage Monitor R/O 7 Address 0x0A 6 5 4 3 2 1 0 0 0 0 0 VPMON[7:0] Default 0 Bits Name 7:0 VPMON 0 0 0 Description Battery voltage (VP) monitor. Represents the VPMON (DOUT) value in the equation in Section 4.8.4. 1000 0000 –128 1111 1111 –1 0000 0001 +1 0111 1111 +127 1000 0001 –127… 0000 0000 0 (default) 0000 0010 +2 … 7.
CS35L32 7.13 ADSP Control 7.13 ADSP Control R/W 7 6 ADSP_DRIVE M/S 0 0 Default Bits 7 Address 0x0F 5 4 3 DATCNF[1:0] 1 2 SHARE 0 Name 0 1 0 — 0 0 0 Description ADSP_ ADSP output drive strength. Selects the drive strength used for the ADSP outputs. These outputs include SDOUT as well as DRIVE SCLK and LRCK when the device is in Master Mode. Table 3-8 lists drive-strength specifications. 0 (Default) 1x 1 0.5x 6 M/S ADSP Master/Slave Mode. Configures the ADSP I/O clocking.
CS35L32 7.16 Interrupt Mask 1 Bits Name 0 OTE_ RLS Description Overtemperature error protection release. Releases (removes) OTE-caused Speaker-Safe Mode if the OTE condition is no longer present, which can be determined by reading OTE (see Section 7.19) twice. 0 (Default) If the OTE condition is present, Speaker-Safe Mode is applied.
CS35L32 7.18 Interrupt Mask 3 7.18 Interrupt Mask 3 R/W 7 6 M_UVLO Address 0x14 5 4 3 2 M_LED2_OPEN M_LED2_SHORT M_LED1_OPEN M_LED1_SHORT 1 0 M_LOWBAT M_BOOST_CURLIM M_BOOST_OVERROR Default 1 1 1 1 1 1 1 1 Interrupt mask register bits serve as a mask for the interrupt sources in the interrupt status registers. Interrupts are described in Section 4.2. Registers at addresses 0x14–0x17 must not be part of a control-port autoincremented read and must be read individually. See Section 4.14.1.
CS35L32 7.20 Interrupt Status 2 (Monitors) 7.20 Interrupt Status 2 (Monitors) R/O 7 6 5 VMON_OVFL IMON_OVFL VPMON_OVFL Address 0x16 4 3 2 1 — 0 PDN_DONE Default x x x x x x x x Interrupt status bits are read only and sticky. Interrupts are described in Section 4.2. Registers at addresses 0x14–0x17 must not be part of a control-port autoincremented read and must be read individually. See Section 4.14.1.
CS35L32 7.22 LED Lighting Status 7.
CS35L32 7.24 LED Movie Mode Current 7.24 LED Movie Mode Current R/W 7 6 — Default Bits 3:2 5 4 3 2 LED_MVCUR[2:0] 0 0 0 — 0 Name 7 6:4 Address 0x1A 0 1 0 LED1_MVEN LED2_MVEN 0 0 0 Description — Reserved LED_ LED Movie Mode drive current.
CS35L32 8 Typical Performance Plots 8 Typical Performance Plots 8.1 System-Level Efficiency and Power-Consumption Plots For all system-level efficiency and power-consumption plots, a simulated speaker load (8 + 33 H) is used; the amplifier PWM outputs (OUT±) contain no EMI filtering. Efficiency calculations are based on RMS power delivered to the load at the generated frequency and include power consumption of both VA and VP. 100 350 90 VBST = VP, VP = 3.0 V VBST = VP, VP = 3.6 V VBST = VP, VP = 4.
CS35L32 40 160 35 140 30 120 VP Idle Power (mW) VP Idle Current (mA) 8.2 Audio Output Typical Performance Plots 25 20 15 10 5 100 80 60 40 20 0 2.5 3 3.5 4 4.5 VP Voltage (V) 5 0 2.5 5.5 3 3.5 4 4.5 VP Voltage (V) 5 5.5 Figure 8-5. Device Idle Power Consumption, Current vs. VP— Figure 8-6. Device Idle Power Consumption, Power vs. VP— VBST = 5.0 V, VBST = VP = 3.6 V VBST = 5.0 V, VBST = VP = 3.6 V 8.
CS35L32 8.3 Monitoring Typical Performance Plots 1 −10 0.8 −20 −30 0.4 PSRR (dB) Amplitude (dBr) 0.6 0.2 0 −0.2 −0.4 −40 −50 −60 −0.6 −70 −0.8 −1 100 1000 Frequency (Hz) −80 10000 Figure 8-9. Frequency Response @ 1 W— Fixed-Boost Mode (VBST = 5 V, Refer to Amplitude @ 1 kHz) 100 1000 Frequency (Hz) 10000 Figure 8-10. VP PSRR Vs. Frequency, VP_ac = 100 mVpk— Bypass Mode (VBST = VP), Fixed-Boost Mode (VBST = 5 V) 8.
CS35L32 8.3 Monitoring Typical Performance Plots í í í í í í í í í í í í í í í í í 9%67 9 9%67 93 í í 7+' 1 G% 7+' 1 G% í í 9%67 9 9%67 93 )UHTXHQF\ +] í Figure 8-13. IMON THD+N Ratio vs. Frequency— Bypass Mode (VBST = VP = 3.6 V, Load = 0.
CS35L32 9 Parameter Definitions 30 −20 8−Ω, 4.7−μH Load 20 8−Ω, 10−μH Load −40 8−Ω, 15−μH Load Amplitude (dBFS) Phase (deg) 8−Ω, 33−μH Load 10 0 −10 −20 −30 −60 −80 −100 −120 100 1000 Frequency (Hz) 10000 Figure 8-17. VMON to IMON Phase vs. Frequency @ 1 W— Fixed-Boost Mode (VBST = 5 V) Load = 8 + 5 H, 8 + 10 H, 8 + 33 H, 8 + 15 H 1 −140 100 1000 Frequency (Hz) 10000 Figure 8-18. IMON FFT, 1 kHz @ Load = 0.
CS35L32 10 Package Dimensions 10 Package Dimensions A A2 X X Ball A1 Location Indicator M A1 Ball A1 Location Indicator Y N Z e c Y Seating plane WAFER BACK SIDE SIDE VIEW b øb Øddd Z X Y Øccc Z d e BUMP SIDE Notes: • Dimensioning and tolerances per ASME Y 14.5M–1994. • The Ball A1 position indicator is for illustration purposes only and may not be to scale.
CS35L32 13 References 13 References 1. NXP Semiconductors (founded by Philips Semiconductor), The I²C-Bus Specification and User Manual. UM10204 Rev. 03, June 19, 2007 http://www.nxp.com 14 Revision History Table 14-1. Revision History Date F2 MAR ‘14 F3 MAY ‘14 F4 JUL ‘14 Changes • Updated values for Boost FET peak-current limit in Table 3-4. • Updated the maximum value for VBST in Table 3-4. • Updated package dimensions in Table 10-1.
