Manual
Table Of Contents
- 1. Pin Descriptions
- 2. Characteristics and Specifications
- 3. Typical Connection Diagram
- 4. Detailed Block Diagram
- 5. Applications
- 5.1 General Description
- 5.2 System Design
- 5.3 Power-Up and Power-Down
- 5.4 Volume & Muting Control Architecture
- 5.5 Volume Controls
- 5.6 Muting Controls
- 5.7 Zero-Crossing Detection
- 5.8 System Serial Control Configuration
- 5.9 I·C/SPI Serial Control Formats
- 6. CS3318 Register Quick Reference
- 7. CS3318 Register Descriptions
- 7.1 Ch 1-8 Volume - Addresses 01h - 08h
- 7.2 ¹dB Control - Address 09h
- 7.3 Mute Control - Address 0Ah
- 7.4 Device Configuration 1 - Address 0Bh (Bit 5)
- 7.5 Device Configuration 2 - Address 0Ch
- 7.6 Channel Power - Address 0Dh
- 7.7 Master Power - Address 0Eh
- 7.8 Freeze Control - Address 0Fh
- 7.9 Master1 Mask - Address 10h
- 7.10 Master1 Volume - Address 11h
- 7.11 Master1 Control - Address 12h
- 7.12 Master2 Mask - Address 13h
- 7.13 Master2 Volume - Address 14h
- 7.14 Master2 Control - Address 15h
- 7.15 Master3 Mask - Address 16h
- 7.16 Master3 Volume - Address 17h
- 7.17 Master3 Control - Address 18h
- 7.18 Group2 Chip Address 19h
- 7.19 Group1 Chip Address 1Ah
- 7.20 Individual Chip Address 1Bh
- 7.21 Chip ID - Address 1Ch
- 8. Parameter Definitions
- 9. Package Dimensions
- 10. Thermal Characteristics and Specifications
- 11. Ordering Information
- 12. Revision History
DS693F1 41
CS3318
7.20 Individual Chip Address 1Bh
7.20.1 Individual Chip Address (Bits 7:1)
SPI Mode Default = 1000000b
I²C Mode Default = See Table 4 on page 27
Function:
These bits set the individual chip address, and may be modified at any time. See “System Serial Con-
trol Configuration” on page 23 and “I²C/SPI Serial Control Formats” on page 27 for more information.
7.20.2 Enable Next Device (Bit 0)
Default = 0
Function:
When set, the CS3318’s enable output pin (ENOut) will be driven high. When cleared, the CS3318’s
enable output pin (ENOut) will be driven low.
7.21 Chip ID - Address 1Ch
This is a Read-Only register.
7.21.1 Chip ID (Bits 7:4)
Default = 0110b
Function:
Chip ID code for the CS3318. Permanently set to 0110.
7.21.2 Chip Revision (Bits 3:0)
Default = xxxxb
Function:
Chip revision code for the CS3318. Encoded as shown in Table 10.
76543210
Ind_Addr6 Ind_Addr5 Ind_Addr4 Ind_Addr3 Ind_Addr2 Ind_Addr1 Ind_Addr0 Enable
76543210
ID3 ID2 ID1 ID0 Rev3 Rev2 Rev1 Rev0
Chip Revision Register Code
A0, B0 0000b
Table 10. Chip Revision Register Codes