Manual
Table Of Contents
- 1. Pin Descriptions
- 2. Characteristics and Specifications
- 3. Typical Connection Diagram
- 4. Detailed Block Diagram
- 5. Applications
- 5.1 General Description
- 5.2 System Design
- 5.3 Power-Up and Power-Down
- 5.4 Volume & Muting Control Architecture
- 5.5 Volume Controls
- 5.6 Muting Controls
- 5.7 Zero-Crossing Detection
- 5.8 System Serial Control Configuration
- 5.9 I·C/SPI Serial Control Formats
- 6. CS3318 Register Quick Reference
- 7. CS3318 Register Descriptions
- 7.1 Ch 1-8 Volume - Addresses 01h - 08h
- 7.2 ¹dB Control - Address 09h
- 7.3 Mute Control - Address 0Ah
- 7.4 Device Configuration 1 - Address 0Bh (Bit 5)
- 7.5 Device Configuration 2 - Address 0Ch
- 7.6 Channel Power - Address 0Dh
- 7.7 Master Power - Address 0Eh
- 7.8 Freeze Control - Address 0Fh
- 7.9 Master1 Mask - Address 10h
- 7.10 Master1 Volume - Address 11h
- 7.11 Master1 Control - Address 12h
- 7.12 Master2 Mask - Address 13h
- 7.13 Master2 Volume - Address 14h
- 7.14 Master2 Control - Address 15h
- 7.15 Master3 Mask - Address 16h
- 7.16 Master3 Volume - Address 17h
- 7.17 Master3 Control - Address 18h
- 7.18 Group2 Chip Address 19h
- 7.19 Group1 Chip Address 1Ah
- 7.20 Individual Chip Address 1Bh
- 7.21 Chip ID - Address 1Ch
- 8. Parameter Definitions
- 9. Package Dimensions
- 10. Thermal Characteristics and Specifications
- 11. Ordering Information
- 12. Revision History
DS693F1 35
CS3318
7.5.2 Zero-Crossing Mode (Bits 1:0)
Default = 01
Function:
These bits control the Zero-Crossing detection mode as shown in Table 9. Refer to the “Zero-Cross-
ing Modes” section on page 22 for more information.
7.6 Channel Power - Address 0Dh
7.6.1 Power Down Channel X (Bit 0 - 7)
Default = 0
Function:
Each respective channel will enter a low-power state whenever this bit is set. A channel’s power-down
bit must be cleared for normal operation to occur.
7.7 Master Power - Address 0Eh
7.7.1 Power Down All (Bit 0)
Default = 1
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default
and must be cleared before normal operation can occur. The control registers remain accessible, and
their contents are retained while the device is in power-down.
ZCMode[1:0] Zero-Crossing Mode
00 Volume changes take effect immediately.
01 Volume changes take effect on a signal zero-crossing. If a zero-crossing is not detected
before the period specified by the TimeOut[2:0] bits has elapsed, the volume change will be
implemented immediately when the time-out period elapses. If the volume setting is
changed again before the original volume change has been implemented, the original
change will be discarded, the time-out period will be reset, and the new volume setting will
take effect when a zero-crossing is detected or the time-out period elapses.
10 Volume changes take effect on a signal zero-crossing. If a zero-crossing is not detected
before the period specified by the TimeOut[2:0] bits has elapsed, the volume change will be
implemented immediately when the time-out period elapses. If the volume setting is
changed again before the original volume change has been implemented, the original vol-
ume change will be implemented immediately upon reception of the new volume change
command, the time-out period will be reset, and the new volume setting will take effect when
a zero-crossing is detected or the time-out period elapses.
11 Reserved
Table 9. Zero-Crossing Mode Settings
76543210
PDN8 PDN7 PDN6 PDN5 PDN4 PDN3 PDN2 PDN1
76543210
Reserved Reserved Reserved Reserved Reserved Reserved Reserved PDN_ALL