Manual
Table Of Contents
- 1. Pin Descriptions
- 2. Characteristics and Specifications
- 3. Typical Connection Diagram
- 4. Detailed Block Diagram
- 5. Applications
- 5.1 General Description
- 5.2 System Design
- 5.3 Power-Up and Power-Down
- 5.4 Volume & Muting Control Architecture
- 5.5 Volume Controls
- 5.6 Muting Controls
- 5.7 Zero-Crossing Detection
- 5.8 System Serial Control Configuration
- 5.9 I·C/SPI Serial Control Formats
- 6. CS3318 Register Quick Reference
- 7. CS3318 Register Descriptions
- 7.1 Ch 1-8 Volume - Addresses 01h - 08h
- 7.2 ¹dB Control - Address 09h
- 7.3 Mute Control - Address 0Ah
- 7.4 Device Configuration 1 - Address 0Bh (Bit 5)
- 7.5 Device Configuration 2 - Address 0Ch
- 7.6 Channel Power - Address 0Dh
- 7.7 Master Power - Address 0Eh
- 7.8 Freeze Control - Address 0Fh
- 7.9 Master1 Mask - Address 10h
- 7.10 Master1 Volume - Address 11h
- 7.11 Master1 Control - Address 12h
- 7.12 Master2 Mask - Address 13h
- 7.13 Master2 Volume - Address 14h
- 7.14 Master2 Control - Address 15h
- 7.15 Master3 Mask - Address 16h
- 7.16 Master3 Volume - Address 17h
- 7.17 Master3 Control - Address 18h
- 7.18 Group2 Chip Address 19h
- 7.19 Group1 Chip Address 1Ah
- 7.20 Individual Chip Address 1Bh
- 7.21 Chip ID - Address 1Ch
- 8. Parameter Definitions
- 9. Package Dimensions
- 10. Thermal Characteristics and Specifications
- 11. Ordering Information
- 12. Revision History

34 DS693F1
CS3318
7.4.3 Channel B = Channel A (Bit 0 - 3)
Default = 0
Function:
When this bit is set, Channel A and Channel B volume levels and muting conditions are controlled by
the Channel A volume and muting register settings, and the Channel B register settings are ignored.
When this bit is cleared, Channel A and Channel B volume and mute settings are independently con-
trolled by the A and B volume and muting bits.
7.5 Device Configuration 2 - Address 0Ch
7.5.1 Zero-Crossing Time-Out Period (Bits 4:2)
Default = 011
Function:
These bits set the zero-crossing time-out period as shown in Table 9. Refer to the “Zero-Crossing
Time-Out” section on page 22 for more information.
Bit Name Bit Setting Control Configuration
Ch8=7 0 Channel 7 and 8 mute and volume settings controlled independently
1 Channel 7 and 8 mute and volume settings controlled by Channel 7 register
settings. Channel 8 register settings are ignored.
Ch6=5 0 Channel 5 and 6 mute and volume settings controlled independently
1 Channel 5 and 6 mute and volume settings controlled by Channel 5 register
settings. Channel 6 register settings are ignored.
Ch4=3 0 Channel 3 and 4 mute and volume settings controlled independently
1 Channel 3 and 4 mute and volume settings controlled by Channel 3 register
settings. Channel 4 register settings are ignored
Ch2=1 0 Channel 1 and 2 mute and volume settings controlled independently
1 Channel 1 and 2 mute and volume settings controlled by Channel 1 register
settings. Channel 2 register settings are ignored
Table 7. Channel B = Channel A Settings
76543210
Reserved Reserved Reserved TimeOut2 TimeOut1 TimeOut0 ZCMode1 ZCMode0
TimeOut[2:0]
Zero-Crossing
Time-Out Period
000 5 ms
001 10 ms
010 15 ms
011 18 ms
100 20 ms
101 30 ms
110 40 ms
111 50 ms
Table 8. Zero-Crossing Time-Out Settings