Manual
Table Of Contents
- 1. Pin Descriptions
- 2. Characteristics and Specifications
- 3. Typical Connection Diagram
- 4. Detailed Block Diagram
- 5. Applications
- 5.1 General Description
- 5.2 System Design
- 5.3 Power-Up and Power-Down
- 5.4 Volume & Muting Control Architecture
- 5.5 Volume Controls
- 5.6 Muting Controls
- 5.7 Zero-Crossing Detection
- 5.8 System Serial Control Configuration
- 5.9 I·C/SPI Serial Control Formats
- 6. CS3318 Register Quick Reference
- 7. CS3318 Register Descriptions
- 7.1 Ch 1-8 Volume - Addresses 01h - 08h
- 7.2 ¹dB Control - Address 09h
- 7.3 Mute Control - Address 0Ah
- 7.4 Device Configuration 1 - Address 0Bh (Bit 5)
- 7.5 Device Configuration 2 - Address 0Ch
- 7.6 Channel Power - Address 0Dh
- 7.7 Master Power - Address 0Eh
- 7.8 Freeze Control - Address 0Fh
- 7.9 Master1 Mask - Address 10h
- 7.10 Master1 Volume - Address 11h
- 7.11 Master1 Control - Address 12h
- 7.12 Master2 Mask - Address 13h
- 7.13 Master2 Volume - Address 14h
- 7.14 Master2 Control - Address 15h
- 7.15 Master3 Mask - Address 16h
- 7.16 Master3 Volume - Address 17h
- 7.17 Master3 Control - Address 18h
- 7.18 Group2 Chip Address 19h
- 7.19 Group1 Chip Address 1Ah
- 7.20 Individual Chip Address 1Bh
- 7.21 Chip ID - Address 1Ch
- 8. Parameter Definitions
- 9. Package Dimensions
- 10. Thermal Characteristics and Specifications
- 11. Ordering Information
- 12. Revision History
30 DS693F1
CS3318
10h Master 1 Mask
M1_Ch8M M1_Ch7M M1_Ch6M M1_Ch5M M1_Ch4M M1_Ch3M M1_Ch2M M1_Ch1M
page 36 111 1 1111
11h Master 1 Vol-
ume
M1_Vol7 M1_Vol6 M1_Vol5 M1_Vol4 M1_Vol3 M1_Vol2 M1_Vol1 M1_Vol0
page 36 110 1 0010
12h Master 1 Con-
trol
Reserved Reserved Reserved Reserved Reserved Reserved M1_Mute M1_Qtr
page 37 000 0 0000
13h Master 2 Mask
M2_Ch8M M2_Ch7M M2_Ch6M M2_Ch5M M2_Ch4M M2_Ch3M M2_Ch2M M2_Ch1M
page 37 111 1 1111
14h Master 2 Vol-
ume
M2_Vol7 M2_Vol6 M2_Vol5 M2_Vol4 M2_Vol3 M2_Vol2 M2_Vol1 M2_Vol0
page 37 110 1 0010
15h Master 2 Con-
trol
Reserved Reserved Reserved Reserved Reserved Reserved M2_Mute M2_Qtr
page 38 000 0 0000
16h Master 3 Mask
M3_Ch8M M3_Ch7M M3_Ch6M M3_Ch5M M3_Ch4M M3_Ch3M M3_Ch2M M3_Ch1M
page 38 111 1 1111
17h Master 3 Vol-
ume
M3_Vol7 M3_Vol6 M3_Vol5 M3_Vol4 M3_Vol3 M3_Vol2 M3_Vol1 M3_Vol0
page 38 110 1 0010
18h Master 3 Con-
trol
Reserved Reserved Reserved Reserved Reserved Reserved M3_Mute M3_Qtr
page 39 000 0 0000
19h Group 2 Chip
Addr
G2_Addr6 G2_Addr5 G2_Addr4 G2_Addr3 G2_Addr2 G2_Addr1 G2_Addr0 EnG2Addr
page 40 100 0 00X0
1Ah Group 1 Chip
Addr
G1_Addr6 G1_Addr5 G1_Addr4 G1_Addr3 G1_Addr2 G1_Addr1 G1_Addr0 EnG1Addr
page 40 100 0 00X0
1Bh Individual Chip
Addr
Ind_Addr6 Ind_Addr5 Ind_Addr4 Ind_Addr3 Ind_Addr2 Ind_Addr1 Ind_Addr0 Enable
page 41 100 0 00X0
1Ch Chip ID
ID3 ID2 ID1 ID0 Rev3 Rev2 Rev1 Rev0
page 41 0 11 0 XXXX
Addr Function 7 6 5 4 3 2 1 0