Manual
Table Of Contents
- 1. Pin Descriptions
- 2. Characteristics and Specifications
- 3. Typical Connection Diagram
- 4. Detailed Block Diagram
- 5. Applications
- 5.1 General Description
- 5.2 System Design
- 5.3 Power-Up and Power-Down
- 5.4 Volume & Muting Control Architecture
- 5.5 Volume Controls
- 5.6 Muting Controls
- 5.7 Zero-Crossing Detection
- 5.8 System Serial Control Configuration
- 5.9 I·C/SPI Serial Control Formats
- 6. CS3318 Register Quick Reference
- 7. CS3318 Register Descriptions
- 7.1 Ch 1-8 Volume - Addresses 01h - 08h
- 7.2 ¹dB Control - Address 09h
- 7.3 Mute Control - Address 0Ah
- 7.4 Device Configuration 1 - Address 0Bh (Bit 5)
- 7.5 Device Configuration 2 - Address 0Ch
- 7.6 Channel Power - Address 0Dh
- 7.7 Master Power - Address 0Eh
- 7.8 Freeze Control - Address 0Fh
- 7.9 Master1 Mask - Address 10h
- 7.10 Master1 Volume - Address 11h
- 7.11 Master1 Control - Address 12h
- 7.12 Master2 Mask - Address 13h
- 7.13 Master2 Volume - Address 14h
- 7.14 Master2 Control - Address 15h
- 7.15 Master3 Mask - Address 16h
- 7.16 Master3 Volume - Address 17h
- 7.17 Master3 Control - Address 18h
- 7.18 Group2 Chip Address 19h
- 7.19 Group1 Chip Address 1Ah
- 7.20 Individual Chip Address 1Bh
- 7.21 Chip ID - Address 1Ch
- 8. Parameter Definitions
- 9. Package Dimensions
- 10. Thermal Characteristics and Specifications
- 11. Ordering Information
- 12. Revision History

24 DS693F1
CS3318
5.8.2 Serial Control within a Multiple-CS3318 System
The CS3318 allows both independent and simultaneous control of up to 128 devices on a shared I²C or
SPI serial control bus. The address of each device is configured by the host controller via the shared serial
control bus. All serial communication, including the configuration of each device’s address, adheres to a
standard I²C or SPI bus protocol.
A device’s Individual device address, which provides read and write access to the device’s internal regis-
ters, should be set to a unique value, different from all other addresses recognized by devices on the serial
communication bus. This address facilitates independent control of each CS3318 on the serial control
bus.
A device’s Group 1 and Group 2 addresses, which provide write-only access to the device’s internal reg-
isters, may be set to the same value across multiple CS3318’s on the shared serial communication bus.
Assigning common Group addresses to multiple devices in a system allows system sub-master and sys-
tem master volume control. For instance, a system containing 8 CS3318’s may configure the Group 1 ad-
dress of the first set of 4 CS3318’s to 10h, the Group 1 address of the second set of 4 CS3318’s to 20h,
and the Group 2 address of all 8 CS3318’s to A0h. In this manner, a serial control data write to address
10h would act as a system sub-master control to the first set of 4 devices, a write to 20h would act as a
system sub-master control to the second set of 4 devices, and a write to A0h would act as a system mas-
ter control to all devices.
By default, the CS3318 will not respond to serial communication when addressed with its Group 1 or
Group 2 address. The CS3318 will only respond to one or both of these addresses if the corresponding
address has been enabled via the control port. To enable a Group address, its corresponding Enable bit,
located in the LSB of its respective Group address register, must be set.
The CS3318 implements an ENOut signal to facilitate the device address configuration process. This sig-
nal is used to hold all but one un-configured device in a reset state. After the Individual device address of
each device has been set, the ENOut signal is used to enable the “next” device in the chain, allowing its
Individual device address to be set. See “SPI Mode Serial Control Configuration” section on page 24 and
“I²C Mode Control Configuration” on page 26 for more information about system configuration in each
communication mode.
5.8.2.1 SPI Mode Serial Control Configuration
Up to 128 CS3318’s sharing the same CS signal may be connected to a common SPI serial control bus.
This shared serial bus is used to assign a unique device address to each device on the bus such that they
may be independently addressed. To implement this method of device address configuration, the devices
must be connected as shown in Figure 9.
Note that the serial control signals CCLK, CS, and MOSI are connected in parallel to each CS3318. The
active low reset output of the system controller is connected to the RESET
input of the first CS3318 in the
chain. The ENOut of the first device is connected to the RESET
input of the second CS3318 whose ENOut
signal is connected to the third CS3318. This pattern of connecting the ENOut of device N to the RESET
μC
CCLK
MOSI
CS
Device 1
CS CCLK
MOSI
RESET ENout Device 2
CS CCLK
MOSI
RESET ENout Device 3
CS CCLK
MOSI
RESET ENoutRST
Figure 9. SPI Serial Control Connections