Manual
Table Of Contents
- 1. Pin Descriptions
- 2. Characteristics and Specifications
- 3. Typical Connection Diagram
- 4. Detailed Block Diagram
- 5. Applications
- 5.1 General Description
- 5.2 System Design
- 5.3 Power-Up and Power-Down
- 5.4 Volume & Muting Control Architecture
- 5.5 Volume Controls
- 5.6 Muting Controls
- 5.7 Zero-Crossing Detection
- 5.8 System Serial Control Configuration
- 5.9 I·C/SPI Serial Control Formats
- 6. CS3318 Register Quick Reference
- 7. CS3318 Register Descriptions
- 7.1 Ch 1-8 Volume - Addresses 01h - 08h
- 7.2 ¹dB Control - Address 09h
- 7.3 Mute Control - Address 0Ah
- 7.4 Device Configuration 1 - Address 0Bh (Bit 5)
- 7.5 Device Configuration 2 - Address 0Ch
- 7.6 Channel Power - Address 0Dh
- 7.7 Master Power - Address 0Eh
- 7.8 Freeze Control - Address 0Fh
- 7.9 Master1 Mask - Address 10h
- 7.10 Master1 Volume - Address 11h
- 7.11 Master1 Control - Address 12h
- 7.12 Master2 Mask - Address 13h
- 7.13 Master2 Volume - Address 14h
- 7.14 Master2 Control - Address 15h
- 7.15 Master3 Mask - Address 16h
- 7.16 Master3 Volume - Address 17h
- 7.17 Master3 Control - Address 18h
- 7.18 Group2 Chip Address 19h
- 7.19 Group1 Chip Address 1Ah
- 7.20 Individual Chip Address 1Bh
- 7.21 Chip ID - Address 1Ch
- 8. Parameter Definitions
- 9. Package Dimensions
- 10. Thermal Characteristics and Specifications
- 11. Ordering Information
- 12. Revision History

22 DS693F1
CS3318
5.7 Zero-Crossing Detection
The CS3318 incorporates comprehensive zero-crossing detection features to provide for noise-free level
transitions. Three zero-crossing detection modes and 8 selectable time-out periods are available for en-
hanced flexibility. Zero-crossing detection and time-out is implemented independently for each channel.
5.7.1 Zero-Crossing Modes
The zero-crossing mode for all channels within the CS3318 are configured via the ZCMode[1:0] bits in the
Device Config 2 register. By default, zero-crossing mode 1 is selected. The zero-crossing modes are de-
tailed in Table 2.
5.7.2 Zero-Crossing Time-Out
When in zero-crossing mode 1 or 2, the zero-crossing time-out period dictates how long the CS3318 will
wait for a signal zero-crossing before implementing the requested volume change without a zero-cross-
ing, thereby allowing the possibility of audible artifacts. The CS3318 provides 8 selectable time-out peri-
ods ranging from 5 ms to 50 ms; these are shown in Table 3.
The zero-crossing time-out period for all channels within the CS3318 is configured via the TimeOut[2:0]
bits in the Device Config 2 register. The time-out period is set to 18 ms (setting 3) by default.
Mode Zero-Crossing Function
0 Volume changes take effect immediately.
1 Volume changes take effect on a signal zero-crossing. If a zero-crossing is not detected before the time-
out period has elapsed, the volume change will be implemented immediately when the time-out period
elapses. If the volume setting is changed again before the original volume change has been imple-
mented, the original change will be discarded, the time-out period will be reset, and the new volume set-
ting will take effect when a zero-crossing is detected or the time-out period elapses.
2 Volume changes take effect on a signal zero-crossing. If a zero-crossing is not detected before the time-
out period has elapsed, the volume change will be implemented immediately when the time-out period
elapses. If the volume setting is changed again before the original volume change has been imple-
mented, the original volume change will be implemented immediately upon reception of the new volume
change command, the time-out period will be reset, and the new volume setting will take effect when a
zero-crossing is detected or the time-out period elapses.
Table 2. Zero-Crossing Modes
Referenced Control Register Location
ZCMode[1:0] ....................... “Zero-Crossing Mode (Bits 1:0)” on page 35
Time-Out Setting Time-Out Period
05ms
110ms
215ms
318ms
420ms
530ms
640ms
750ms
Table 3. Zero-Crossing Time-Out Periods
Referenced Control Register Location
TimeOut[2:0] ....................... “Zero-Crossing Time-Out Period (Bits 4:2)” on page 34