Manual
Table Of Contents
- 1. Pin Descriptions
- 2. Characteristics and Specifications
- 3. Typical Connection Diagram
- 4. Detailed Block Diagram
- 5. Applications
- 5.1 General Description
- 5.2 System Design
- 5.3 Power-Up and Power-Down
- 5.4 Volume & Muting Control Architecture
- 5.5 Volume Controls
- 5.6 Muting Controls
- 5.7 Zero-Crossing Detection
- 5.8 System Serial Control Configuration
- 5.9 I·C/SPI Serial Control Formats
- 6. CS3318 Register Quick Reference
- 7. CS3318 Register Descriptions
- 7.1 Ch 1-8 Volume - Addresses 01h - 08h
- 7.2 ¹dB Control - Address 09h
- 7.3 Mute Control - Address 0Ah
- 7.4 Device Configuration 1 - Address 0Bh (Bit 5)
- 7.5 Device Configuration 2 - Address 0Ch
- 7.6 Channel Power - Address 0Dh
- 7.7 Master Power - Address 0Eh
- 7.8 Freeze Control - Address 0Fh
- 7.9 Master1 Mask - Address 10h
- 7.10 Master1 Volume - Address 11h
- 7.11 Master1 Control - Address 12h
- 7.12 Master2 Mask - Address 13h
- 7.13 Master2 Volume - Address 14h
- 7.14 Master2 Control - Address 15h
- 7.15 Master3 Mask - Address 16h
- 7.16 Master3 Volume - Address 17h
- 7.17 Master3 Control - Address 18h
- 7.18 Group2 Chip Address 19h
- 7.19 Group1 Chip Address 1Ah
- 7.20 Individual Chip Address 1Bh
- 7.21 Chip ID - Address 1Ch
- 8. Parameter Definitions
- 9. Package Dimensions
- 10. Thermal Characteristics and Specifications
- 11. Ordering Information
- 12. Revision History

2 DS693F1
CS3318
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................................ 5
2. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 7
SPECIFIED OPERATING CONDITIONS .................................................................................................... 7
ABSOLUTE MAXIMUM RATINGS............................................................................................................... 7
ANALOG CHARACTERISTICS ................................................................................................................... 8
DIGITAL INTERFACE CHARACTERISTICS...............................................................................................9
MUTE SWITCHING CHARACTERISTICS ..................................................................................................9
CONTROL PORT SWITCHING CHARACTERISTICS - I²C FORMAT...................................................... 10
CONTROL PORT SWITCHING CHARACTERISTICS - SPI™ FORMAT ................................................. 11
3. TYPICAL CONNECTION DIAGRAM ................................................................................................. 12
4. DETAILED BLOCK DIAGRAM .......................................................................................................... 13
5. APPLICATIONS ................................................................................................................................. 14
5.1 General Description ..................................................................................................................... 14
5.2 System Design ............................................................................................................................ 14
5.2.1 Analog Inputs .................................................................................................................... 14
5.2.2 Analog Outputs .................................................................................................................. 15
5.2.3 Recommended Layout, Grounding, and Power Supply Decoupling ................................. 15
5.3 Power-Up and Power-Down ........................................................................................................ 15
5.3.1 Recommended Power-Up Sequence ................................................................................ 16
5.3.2 Recommended Power-Down Sequence ........................................................................... 16
5.4 Volume & Muting Control Architecture ........................................................................................ 17
5.4.1 Control Mapping Matrix ..................................................................................................... 17
5.4.2 Volume & Muting Control Implementation ......................................................................... 18
5.5 Volume Controls .......................................................................................................................... 19
5.5.1 Individual Channel Volume Controls ................................................................................. 19
5.5.2 Master Volume Controls .................................................................................................... 19
5.5.3 Volume Limits .................................................................................................................... 20
5.6 Muting Controls ........................................................................................................................... 21
5.6.1 Individual Channel Mute Controls ..................................................................................... 21
5.6.2 Master Mute Controls ........................................................................................................ 21
5.6.3 Hardware Mute Control ..................................................................................................... 21
5.7 Zero-Crossing Detection .............................................................................................................. 22
5.7.1 Zero-Crossing Modes ........................................................................................................ 22
5.7.2 Zero-Crossing Time-Out .................................................................................................... 22
5.8 System Serial Control Configuration ........................................................................................... 23
5.8.1 Serial Control within a Single-CS3318 System ................................................................. 23
5.8.2 Serial Control within a Multiple-CS3318 System ............................................................... 24
5.8.2.1 SPI Mode Serial Control Configuration .......................................................................................... 24
5.8.2.2 I²C Mode Control Configuration ..................................................................................................... 26
5.9 I²C/SPI Serial Control Formats .................................................................................................... 27
5.9.1 I²C Mode ............................................................................................................................ 27
5.9.2 SPI Mode ........................................................................................................................... 28
6. CS3318 REGISTER QUICK REFERENCE ........................................................................................ 29
7. CS3318 REGISTER DESCRIPTIONS ................................................................................................ 31
7.1 Ch 1-8 Volume - Addresses 01h - 08h ........................................................................................ 31
7.1.1 Volume Control (Bits 7:0) .................................................................................................. 31
7.2 ¼ dB Control - Address 09h ........................................................................................................ 32
7.2.1 ¼ dB Control (Bit 0 - 7) ...................................................................................................... 32
7.3 Mute Control - Address 0Ah ........................................................................................................ 33
7.3.1 Mute Channel X (Bit 0 - 7) ................................................................................................. 33
7.4 Device Configuration 1 - Address 0Bh (Bit 5) ..............................................................................33
7.4.1 Enable MUTE Input (Bit 5) ..............................................................................................
.. 33