Manual
Table Of Contents
- 1. Pin Descriptions
- 2. Characteristics and Specifications
- 3. Typical Connection Diagram
- 4. Detailed Block Diagram
- 5. Applications
- 5.1 General Description
- 5.2 System Design
- 5.3 Power-Up and Power-Down
- 5.4 Volume & Muting Control Architecture
- 5.5 Volume Controls
- 5.6 Muting Controls
- 5.7 Zero-Crossing Detection
- 5.8 System Serial Control Configuration
- 5.9 I·C/SPI Serial Control Formats
- 6. CS3318 Register Quick Reference
- 7. CS3318 Register Descriptions
- 7.1 Ch 1-8 Volume - Addresses 01h - 08h
- 7.2 ¹dB Control - Address 09h
- 7.3 Mute Control - Address 0Ah
- 7.4 Device Configuration 1 - Address 0Bh (Bit 5)
- 7.5 Device Configuration 2 - Address 0Ch
- 7.6 Channel Power - Address 0Dh
- 7.7 Master Power - Address 0Eh
- 7.8 Freeze Control - Address 0Fh
- 7.9 Master1 Mask - Address 10h
- 7.10 Master1 Volume - Address 11h
- 7.11 Master1 Control - Address 12h
- 7.12 Master2 Mask - Address 13h
- 7.13 Master2 Volume - Address 14h
- 7.14 Master2 Control - Address 15h
- 7.15 Master3 Mask - Address 16h
- 7.16 Master3 Volume - Address 17h
- 7.17 Master3 Control - Address 18h
- 7.18 Group2 Chip Address 19h
- 7.19 Group1 Chip Address 1Ah
- 7.20 Individual Chip Address 1Bh
- 7.21 Chip ID - Address 1Ch
- 8. Parameter Definitions
- 9. Package Dimensions
- 10. Thermal Characteristics and Specifications
- 11. Ordering Information
- 12. Revision History

18 DS693F1
CS3318
Combining the multiple group addressing capabilities of the CS3318 (as detailed in section 5.8.2 on
page 24) with the internal master control mapping abilities described above allows the configuration and
direct addressing of multiple logical groups of channels across multiple CS3318 devices within a system.
5.4.2 Volume & Muting Control Implementation
Figure 6 below diagrams in detail the volume and muting control architecture of the CS3318 for an arbi-
trary channel ‘N’.
This diagram incorporates all volume and muting control concepts presented in sections 5.4 - 5.6; it is
included as a reference and will serve to corroborate the information presented in these sections.
Referenced Control Register Location
Master X Mask .................... “Master 1 Mask - Address 10h” on page 36
“Master 2 Mask - Address 13h” on page 37
“Master 3 Mask - Address 16h” on page 38
Limit Volume Result
-96 dB to +22 dB
Ch. N - Volume
Register N
Ch. N - ¼ dB Control
Register 09h, Bit N-1
Σ
Ch. N Master 2 Mask
Register 13h, Bit N-1
Hardware Mute Input
Pin 4
Master 1 - Mute
Register 12h, Bit 1
Mute
Channel N - Mute
Register 0Ah, Bit N-1
Master 3 - Mute
Register 18h, Bit 1
Master 2 - Mute
Register 15h, Bit 1
Ch. N Master 1 Mask
Register 10h, Bit N-1
Ch. N Master 3 Mask
Register 16h, Bit N-1
_
+
Channel N
REFI
REFO
Input
Output
Σ
Mask 1
Mask 2
Mask 3
Master 1 - Volume
Register 11h
Master 1 - ¼ dB
Register 12h, Bit 0
Σ
Master 2 - Volume
Register 14h
Master 2 - ¼ dB
Register 15h, Bit 0
Σ
Mask 2
Master 3 - Volume
Register 17h
Master 3 - ¼ dB
Register 18h, Bit 0
Σ
Mask 3
Mask 1
Mask 1
Mask 3
Σ
Σ
Mask 2
Mute Input Enable
Register 0Bh, Bit 5
Mute if result is
less than -96 dB.
Figure 6. Volume & Muting Control Implementation