Manual
Table Of Contents
- 1. Pin Descriptions
- 2. Characteristics and Specifications
- 3. Typical Connection Diagram
- 4. Detailed Block Diagram
- 5. Applications
- 5.1 General Description
- 5.2 System Design
- 5.3 Power-Up and Power-Down
- 5.4 Volume & Muting Control Architecture
- 5.5 Volume Controls
- 5.6 Muting Controls
- 5.7 Zero-Crossing Detection
- 5.8 System Serial Control Configuration
- 5.9 I·C/SPI Serial Control Formats
- 6. CS3318 Register Quick Reference
- 7. CS3318 Register Descriptions
- 7.1 Ch 1-8 Volume - Addresses 01h - 08h
- 7.2 ¹dB Control - Address 09h
- 7.3 Mute Control - Address 0Ah
- 7.4 Device Configuration 1 - Address 0Bh (Bit 5)
- 7.5 Device Configuration 2 - Address 0Ch
- 7.6 Channel Power - Address 0Dh
- 7.7 Master Power - Address 0Eh
- 7.8 Freeze Control - Address 0Fh
- 7.9 Master1 Mask - Address 10h
- 7.10 Master1 Volume - Address 11h
- 7.11 Master1 Control - Address 12h
- 7.12 Master2 Mask - Address 13h
- 7.13 Master2 Volume - Address 14h
- 7.14 Master2 Control - Address 15h
- 7.15 Master3 Mask - Address 16h
- 7.16 Master3 Volume - Address 17h
- 7.17 Master3 Control - Address 18h
- 7.18 Group2 Chip Address 19h
- 7.19 Group1 Chip Address 1Ah
- 7.20 Individual Chip Address 1Bh
- 7.21 Chip ID - Address 1Ch
- 8. Parameter Definitions
- 9. Package Dimensions
- 10. Thermal Characteristics and Specifications
- 11. Ordering Information
- 12. Revision History

DS693F1 17
CS3318
5.4 Volume & Muting Control Architecture
The CS3318’s volume and muting control architecture provides the ability to control each channel on an
individual and master basis.
Individual control allows the volume and mute state of a single channel to be changed independently from
all other channels within the device. The CS3318 provides 8 individual volume and muting controls, each
permanently assigned to one channel within the device.
Master control allows the volume and mute state of multiple channels to be changed simultaneously with a
single register write. The CS3318 provides three master controls, and each may be configured to affect any
group of channels within a device.
Refer to the “Volume Controls” section beginning on page 19 and the “Muting Controls” section beginning
on page 21 for an in-depth description of the operation of the available controls.
5.4.1 Control Mapping Matrix
Figure 5 shows a conceptual drawing of the CS3318’s internal control-to-channel mapping matrix. Notice
that the individual channel controls are fixed to their respective channel, and the master controls may be
configured to affect any or all channels within the device.
Each master control has a corresponding Master X Mask register which allows the user to select which
channels are affected by the control. By default, each master control is configured to affect all channels
within the device. Referring to Figure 5 below, each configurable connection shown may be made and
broken by setting or clearing its corresponding bit in the control’s Master X Mask register.
The contents of the Master X Mask registers determine which channels are affected by both a master con-
trol’s volume and mute settings. Refer to the “Volume & Muting Control Implementation” section on
page 18 for a complete diagram of the CS3318’s volume and muting control architecture.
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Master 1
Master 2
Master 3
Control Mapping Matrix
Volume & Muting
Controls
Ch. 1 Ch. 2 Ch. 3 Ch. 4 Ch. 5 Ch. 6 Ch. 7 Ch. 8
Configurable ConnectionFixed Connection
Analog
Gain/Attenuation
Stages
Figure 5. CS3318 Control Mapping Matrix