Manual

DS693F1 11
CS3318
CONTROL PORT SWITCHING CHARACTERISTICS - SPI™ FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
=20pF)
8. Data must be held for sufficient time to bridge the transition time of CCLK.
9. For f
sck
<1 MHz.
Parameter Symbol Min Max Unit
CCLK Clock Frequency f
sck
06.0MHz
RESET
Rising Edge to CS Falling t
srs
100 - ns
CS
High Time Between Transmissions t
csh
1.0 - μs
CS
Falling to CCLK Edge t
css
20 - ns
CCLK Low Time t
scl
66 - ns
CCLK High Time t
sch
66 - ns
CDIN to CCLK Rising Setup Time t
dsu
40 - ns
CCLK Rising to DATA Hold Time (Note 8) t
dh
15 - ns
Rise Time of CCLK and CDIN (Note 9) t
r2
- 100 ns
Fall Time of CCLK and CDIN (Note 9) t
f2
- 100 ns
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
MOSI
t
css
t
csh
RESET
t
srs
CCLK
Figure 2. Control Port Timing - SPI Format