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Cirrus Logic, Inc.

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CS3310

Stereo Digital Volume Control

Features

z Complete Digital Volume Control

— 2 Independent Channels

— Serial Control

— 0.5 dB Step Size

z Wide Adjustable Range

— -95.5 dB Attenuation

— +31.5 dB Gain

z Low Distortion & Noise

— 0.001% THD+N

— 116 dB Dynamic Range

z Noise Free Level Transitions

z Channel-to-Channel Crosstalk Better Than

110 dB

Description

The CS3310 is a complete stereo digital volume control

designed specifically for audio systems. It features a 16-

bit serial interface that controls two independent, low-

distortion audio channels.

The CS3310 includes an array of well-matched resistors

and a low noise active output stage that is capable of

driving a 600 Ω load. A total adjustable range of 127 dB,

in 0.5 dB steps, is achieved through 95.5 dB of attenua-

tion and 31.5 dB of gain.

The simple 3-wire interface provides daisy-chaining of

multiple CS3310's for multi-channel audio systems.

The device operates from ±5 V supplies and has an in-

put/output voltage range of ±3.75 V.

ORDERING INFORMATION

CS3310-KS 0° to 70° C 16-pin Plastic SOIC

CS3310-KSZ, Lead Free 0° to 70° C 16-pin Plastic SOIC

AINL

AGNDL

MUX

AINR

AGNDR

MUX

Control

Serial to

Parallel

AOUTL

MUTE

ZCEN

SDATAI

SDATAO

SCLK

AOUTR

DGND

VD+

VA-

VA+

SEPTEMBER '05

DS82F1

Summary of content (17 pages)

PAGE 1
CS3310 Stereo Digital Volume Control Features z Complete Description Digital Volume Control The CS3310 is a complete stereo digital volume control designed specifically for audio systems. It features a 16bit serial interface that controls two independent, lowdistortion audio channels. — 2 Independent Channels — Serial Control — 0.5 dB Step Size z Wide The CS3310 includes an array of well-matched resistors and a low noise active output stage that is capable of driving a 600 Ω load.
PAGE 2
CS3310 ANALOG CHARACTERISTICS (TA = 25 °C, VA+, VD+ = 5 V ± 5%; VA- = -5V ± 5%; Rs = 0; RL = 2 kΩ; CL = 20 pF; 10 Hz to 20 kHz Measurement Bandwidth; unless otherwise specified) Parameter Symbol Min Typ Max Unit Step Size - 0.5 - dB Gain Error (31.5 dB Gain) - ±0.05 - dB Gain Matching Between Channels - ±0.05 - dB DC Characteristics Input Resistance RIN 8 10 - kΩ Input Capacitance CIN - 10 - pF THD+N - 0.001 .0025 % 110 116 - dB (VA-)+1.25 - (VA+)-1.
PAGE 3
CS3310 DIGITAL CHARACTERISTICS (TA = 25 °C, VA+ , VD+ = 5V ± 5%, VA- = -5V ± 5% ) Parameter Symbol Min Typ Max Unit High-Level Input Voltage VIH 2.0 - VD+0.3 V Low-Level Input Voltage VIL -0.3 - +0.8 V High-Level Output Voltage (I O = 200µA) VOH VD-1.0 - - V Low-Level Output Voltage (I O = 3.2mA) VOL - - 0.4 V Iin - 1.
PAGE 4
CS3310 RECOMMENDED OPERATING CONDITIONS (DGND = 0V; all voltages with respect to ground) Parameter Symbol Min Typ Max Unit VD+ VA+ VA - 4.75 4.75 -4.75 -0.3 5.0 5.0 -5.0 - VA+ 5.25 -5.25 0.0 V V V V TA 0 25 70 °C DC Power Supplies: Positive Digital Positive Analog Negative Analog (VD+) - (VA+) (Note 3) Ambient Operating Temperature Notes: 3. Applying power to VD+ prior to VA+ creates a SCR latch-up condition. Refer to Figure 2 for the recommended power connections.
PAGE 5
CS3310 ** 10 10 µ F + 0.1 µ F 1 ZCEN 4 12 VD+ + 0.1 µ F +5V ANALOG 10 µ F VA+ 0.1 µ F 13 2 VA- CS 3 CONTROLLER 0.1 µ F SCLK 16 AUDIO SOURCE -5V ANALOG CS3310 7 SDATAO MUTE * AINL AOUTL 9 + SDATAI 6 8 10 µ F 14 11 AOUTR AINR DGND AGNDL AGNDR 5 15 10 47 kΩ TO ANOTHER CS3310 OR CONTROLLER AUDIO OUTPUTS *Required to terminate SDATAI due to high impedance state of SDATAO when CS is high. **Refer to Note 3. Figure 2.
PAGE 6
CS3310 GENERAL DESCRIPTION The CS3310 is a stereo, digital volume control designed for audio systems. The levels of the left and right analog input channels are set by a 16-bit serial data word; the first 8 bits address the right channel and the remaining 8 bits address the left channel, as detailed in Table 1. Resistor values are decoded to 0.5 dB resolution by an internal multiplexer for a total attenuation range of -95.5 dB. An output amplifier stage provides a programmable gain of up to 31.5 dB in 0.
PAGE 7
CS3310 CS SCLK SDATAI R7 R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0 SDATAO R7 R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0 L0 = Left Channel Least Significant Bit R0 = Right Channel Least Significant Bit L7 = Left Channel Most Significant Bit R7 = Right Channel Most Significant Bit SDATAI is latched internally on the rising edge of SCLK SDATAO transitions after the falling edge of SCLK SDATAO bits reflect the data previously loaded into the CS3310 Figure 3.
PAGE 8
CS3310 Changing the Analog Output Level Care has been taken to ensure that there are no audible artifacts in the analog output signal during volume control changes. The gain/attenuation changes of the CS3310 occur at zero crossings to eliminate glitches during level transitions. The zero crossing for the left channel is the voltage potential at the AGNDL pin; the voltage potential at the AGNDR pin defines the right channel zero crossing.
PAGE 9
CS3310 a source of distortion if the source impedance becomes appreciable relative to the reversed biased diode capacitance. Source impedances equal to or less than 600 ohms will avoid this distortion mechanism for the CS3310. Mute Muting can be achieved by either hardware or software control. Hardware muting is accomplished via the MUTE input and software muting by loading all zeroes into the volume control register.
PAGE 10
CS3310 PCB Layout, Grounding and Power Supply Decoupling As with any high performance device which contains both analog and digital circuitry, careful attention to power supply and grounding arrangements must be observed to optimize performance. Figure 2 shows the recommended power arrangements with VA+ connected to a clean +5 volt supply and VA- connected to a clean -5 volt supply.
PAGE 11
CS3310 Figure 7 is a 16k FFT plot demonstrating the crosstalk performance of the CS3310 at 20 kHz. Both channels were set to unity gain. The right channel input is grounded with the left channel driven to 2.65 Vrms output at 20 kHz. The FFT plot is of the right channel output. This indicates channel to channel crosstalk of -130 dB at 20 kHz. Figure 10 is a series of plots which display the unity-gain THD+N vs. Frequency for 600 Ω, 2 kΩ and infinite load conditions. The output was set to 2 Vrms.
PAGE 12
CS3310 . THD+N% vs AMPL (Vrms) AMPL (dBr) vs FREQ (Hz) 1 0 -20 -40 .1 -60 -80 .01 -100 -120 .001 -140 -160 .0001 0.1 1 3 -180 20.00 2.06k 4.11k 6.15k 8.19k 10.2k 12.3k 14.3k 16.4k 18.4k 20.5k 22.5k Figure 6. THD+N vs. AMP Figure 7. 20 kHz Crosstalk AMPL (dBr) vs FREQ (Hz) AMPL (dBr) vs FREQ (Hz) 1.0 1.0 0.5 0.5 0.0 0.0 -0.5 -0.5 -1.0 -1.0 -1.5 -1.5 -2.0 -2.0 10 100 10k 1k 100k 200k Figure 8. Frequency Response Full Scale Input 0.1000 10 100 10k 1k 100k 200k Figure 9.
PAGE 13
CS3310 PIN DESCRIPTION Zero Crossing Enable ZCEN 1 16 AINL Left Channel Input Chip Select CS 2 15 AGNDL Left Analog Ground Serial Data Input SDATAI 3 14 AOUTL Left Channel Output Positive Digital Power VD+ 4 13 VA- Negative Analog Power Digital Ground DGND 5 12 VA+ Positive Analog Power Serial Clock Input SCLK 6 11 AOUTR Right Channel Output Serial Data Output SDATAO 7 10 AGNDR Right Analog Ground Mute MUTE 8 9 AINR Right Channel Input Power Supply Connection
PAGE 14
CS3310 Analog Inputs and Outputs AINL, AINR - Left and Right Channel Analog Inputs, Pins 16, 9. Analog input connections for the left and right channels. Nominally ±3.75 volts for a full scale input. AOUTL, AOUTR - Left and Right Channel Analog Outputs, Pins 14, 11. Analog outputs for the left and right channels. Nominally ±3.75 volts for a full scale output. Digital Pins SDATAI - Serial Data Input, Pin 3. Serial input data that sets the analog output level of the left and right channels.
PAGE 15
CS3310 ZCEN - Zero Crossing Enable, Pin 1. This pin enables or disables the zero crossing detection and time-out function used during analog output level transitions. A high level on this pin enables the zero crossing detection function. A low level on this pin disables the zero crossing detection. PARAMETER DEFINITIONS Dynamic Range Full scale (RMS) signal to broadband noise ratio. The broadband noise is measured over the specified bandwidth with the input grounded. Units in decibels.
PAGE 16
CS3310 PACKAGE DIMENSIONS 16L SOIC (300 MIL BODY) PACKAGE DRAWING E H 1 b c D SEATING PLANE ∝ A L e A1 INCHES DIM A A1 B C D E e H L ∝ MIN 0.093 0.004 0.013 0.009 0.398 0.291 0.040 0.394 0.016 0° MAX 0.104 0.012 0.020 0.013 0.413 0.299 0.060 0.419 0.050 8° MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 7.40 7.60 1.02 1.52 10.00 10.65 0.40 1.
PAGE 17
CS3310 Revision Date PP1 April 1991 PP2 December 1992 Update specifications PP3 February 1999 Update specifications PP4 F1 July 2004 September 2005 Changes Initial release Update specifications and bring into new template. Add lead free part. Added “Lead Free” to Ordering Information on front page. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.