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Fractional-N Frequency Synthesizer

Features

 Delta-Sigma Fractional-N Frequency Synthesis

– Generates a Low Jitter 6 - 75 MHz Clock

from an 8 - 75 MHz Reference Clock

 Highly Accurate PLL Multiplication Factor

– Maximum Error Less Than 1 PPM

 I²C™ / SPI™ Control Port

 Configurable Auxiliary Output

– Buffered Reference Clock

– PLL Lock Indication

– Duplicate PLL Output

 Flexible Sourcing of Reference Clock

– External Oscillator or Clock Source

– Supports Inexpensive Local Crystal

 Minimal Board Space Required

– No External Analog Loop-filter

Components

General Description

The CS2200-CP is an extremely versatile system clock-

ing device that utilizes a programmable phase lock loop.

The CS2200-CP is based on an analog PLL architec-

ture comprised of a Delta-Sigma Fractional-N

Frequency Synthesizer. This architecture allows for fre-

quency synthesis and clock generation from a stable

reference clock.

The CS2200-CP supports both I²C and SPI for full soft-

ware control.

The CS2200-CP is available in a 10-pin MSOP package

in Commercial (-10°C to +70°C) and Automotive (-40°C

to +85°C) grades.

Customer development kits are also available for device

evaluation. Please see “Ordering Information” on

page 25 for complete details.

I²C / SPI

Auxiliary

Output

6 to 75 MHz

PLL Output

3.3 V

I²C/SPI Software

Control

8 MHz to 75 MHz

Low-Jitter Timing

Reference

Output to Input

Clock Ratio

Timing Reference

PLL Output

PLL Lock Indicator

Fractional-N

Divider

Voltage Controlled

Oscillator

Internal

Loop Filter

Phase

Comparator

Delta-Sigma

Modulator

MAY '10

DS759F2

CS2200-CP

Summary of content (26 pages)

PAGE 1
CS2200-CP Fractional-N Frequency Synthesizer Features General Description  Delta-Sigma Fractional-N Frequency Synthesis –      Generates a Low Jitter 6 - 75 MHz Clock from an 8 - 75 MHz Reference Clock Highly Accurate PLL Multiplication Factor – Maximum Error Less Than 1 PPM I²C™ / SPI™ Control Port Configurable Auxiliary Output – Buffered Reference Clock – PLL Lock Indication – Duplicate PLL Output Flexible Sourcing of Reference Clock – External Oscillator or Clock Source – Supports Inexpensiv
PAGE 2
CS2200-CP TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .......................................
PAGE 3
CS2200-CP 8.7 Function Configuration 2 (Address 17h) ........................................................................................ 22 8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 22 9. CALCULATING THE USER DEFINED RATIO .................................................................................... 23 9.1 12.20 Format .......................................................................................................
PAGE 4
CS2200-CP 1. PIN DESCRIPTION VD 1 10 SDA/CDIN GND 2 9 SCL/CCLK CLK_OUT 3 8 AD0/CS AUX_OUT 4 7 XTI/REF_CLK TST_IN 5 6 XTO Pin Name # Pin Description VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections. GND 2 Ground (Input) - Ground reference. CLK_OUT 3 PLL Clock Output (Output) - PLL clock output.
PAGE 5
CS2200-CP 2. TYPICAL CONNECTION DIAGRAM Note1 Notes: 1. Resistors required for I2C operation. 0.1 µF 2 kΩ 1 µF +3.3 V 2 kΩ VD SCL/CCLK System MicroController SDA/CDIN CLK_OUT AD0/CS To circuitry which requires a low-jitter clock CS2200-CP AUX_OUT 1 or 2 XTI/REF_CLK XTO GND Low-Jitter Timing Reference To other circuitry or Microcontroller TST_IN REF_CLK 1 N.C. x XTO or Crystal XTI 2 XTO 40 pF 40 pF Figure 1.
PAGE 6
CS2200-CP 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. (Note 1) Parameters DC Power Supply Symbol Min Typ Max Units VD 3.1 3.3 3.5 V TAC TAD -10 -40 - +70 +85 °C °C Ambient Operating Temperature (Power Applied) Commercial Grade Automotive Grade Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability.
PAGE 7
CS2200-CP AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); TA = -40°C to +85°C (Automotive Grade); CL = 15 pF.
PAGE 8
CS2200-CP CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; CL = 20 pF. Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz Bus Free-Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low Time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.
PAGE 9
CS2200-CP CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; CL = 20 pF. Parameter Symbol Min Max Unit fccllk - 6 MHz tspi 500 - ns CS High Time Between Transmissions tcsh 1.
PAGE 10
CS2200-CP 4. ARCHITECTURE OVERVIEW 4.1 Delta-Sigma Fractional-N Frequency Synthesizer The core of the CS2200 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolution for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to quickly tune to a new frequency. In very simplistic terms, the Fractional-N Frequency Synthesizer multiplies the Timing Reference Clock by the value of N to generate the PLL output clock.
PAGE 11
CS2200-CP 5. APPLICATIONS 5.1 Timing Reference Clock Input The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an external crystal in conjunction with the internal oscillator. In order to maintain a stable and low-jitter PLL output the timing reference clock must also be stable and low-jitter; the quality of the timing reference clock directly affects the performance of the PLL and hence the quality of the PLL output. 5.1.
PAGE 12
CS2200-CP 5.1.2 Crystal Connections (XTI and XTO) An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode parallel resonant crystal must be connected between the XTI and XTO pins as shown in Figure 7. As shown, nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer to the “AC Electrical Characteristics” on page 7 for the allowed crystal frequency range. XTI 40 pF XTO 40 pF Figure 7.
PAGE 13
CS2200-CP 5.2.2 Ratio Modifier (R-Mod) The Ratio Modifier is used to internally multiply/divide the RUD (the Ratio stored in the register space remains unchanged). The available options for RMOD are summarized in Table 1 on page 13. The R-Mod value selected by RModSel[2:0] is always used in the calculation for the Effective Ratio (REFF), see “Effective Ratio (REFF)” on page 13.
PAGE 14
CS2200-CP 5.2.4 Ratio Configuration Summary The RUD is the user defined ratio stored in the register space. R-Mod is applied if selected. The user defined ratio, and ratio modifier make up the effective ratio REFF, the final calculation used to determine the output to input clock ratio. The effective ratio is then corrected for the internal dividers.
PAGE 15
CS2200-CP 5.4 Auxiliary Output The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 10, to one of three signals: reference clock (RefClk), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is controlled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is then used to control the output driver type and polarity of the LOCK signal (see section 8.6.1 on page 22).
PAGE 16
CS2200-CP thesizer. This includes all the bits shown in Figure 8 on page 14. • 5.6 Any discontinuities on the Timing Reference Clock, REF_CLK. Required Power Up Sequencing • Apply power to the device. The output pins will remain low until the device is configured with a valid ratio via the control port. • Write the desired operational configurations. The EnDevCfg1 and EnDevCfg2 bits must be set to 1 during the initialization register writes; the order does not matter.
PAGE 17
CS2200-CP CS 0 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15 16 17 CCLK CHIP ADDRESS 1 CDIN 0 0 1 1 1 MAP BYTE 1 0 6 INCR 5 4 3 DATA +n DATA 2 1 0 7 6 1 7 0 6 1 0 Figure 11. Control Port Timing in SPI Mode The signal timings for a read and write cycle are shown in Figure 12 and Figure 13. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high.
PAGE 18
CS2200-CP Send stop condition, aborting write. Send start condition. Send 100111x1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. 6.
PAGE 19
CS2200-CP 8. REGISTER DESCRIPTIONS In I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Reserved” registers must maintain their default state to ensure proper functional operation. The default state of each bit after a power-up sequence or reset is indicated by the shaded row in the bit decode table and in the “Register Quick Reference” on page 18.
PAGE 20
CS2200-CP 8.2.3 PLL Clock Output Disable (ClkOutDis) This bit controls the output driver for the CLK_OUT pin. 8.3 ClkOutDis Output Driver State 0 CLK_OUT output driver enabled. 1 CLK_OUT output driver set to high-impedance. Application: “PLL Clock Output” on page 14 Device Configuration 1 (Address 03h) 7 RModSel2 8.3.
PAGE 21
CS2200-CP 8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) This bit, in conjunction with EnDevCfg2, configures the device for control port mode. These EnDevCfg bits can be set in any order and at any time during the control port access sequence, however they must both be set before normal operation can occur. EnDevCfg1 Register State 0 Disabled. 1 Enabled. Application: “SPI / I²C Control Port” on page 16 Note: EnDevCfg2 must also be set to enable control port mode.
PAGE 22
CS2200-CP 8.6 Function Configuration 1 (Address 16h) 7 Reserved 8.6.1 6 AuxLockCfg 5 Reserved 4 RefClkDiv1 3 RefClkDiv0 2 Reserved 1 Reserved 0 Reserved AUX PLL Lock Output Configuration (AuxLockCfg) When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this bit is disregarded.
PAGE 23
CS2200-CP 9. CALCULATING THE USER DEFINED RATIO Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User Defined Ratio. This section is for those who are not interested in the software or who are developing their systems without the aid of the evaluation kit. Most calculators do not interpret the fixed point binary representation which the CS2200 uses to define the output to input clock ratio (see Section 5.2.
PAGE 24
CS2200-CP 10.PACKAGE DIMENSIONS 10L MSOP (3 mm BODY) PACKAGE DRAWING (Note 1) N D E11 c E A2 A ∝ e b A1 SIDE VIEW 1 2 3 END VIEW L SEATING PLANE L1 TOP VIEW DIM MIN INCHES NOM A A1 A2 b c D E E1 e L L1 -0 0.0295 0.0059 0.0031 ----0.0157 -- -----0.1181 BSC 0.1929 BSC 0.1181 BSC 0.0197 BSC 0.0236 0.0374 REF MAX 0.0433 0.0059 0.0374 0.0118 0.0091 ----0.0315 -- MIN MILLIMETERS NOM NOTE MAX -0 0.75 0.15 0.08 ----0.40 -- -----3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 0.60 0.95 REF 1.10 0.
PAGE 25
CS2200-CP 11.
PAGE 26
CS2200-CP Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).