User guide

CS2100-OTP
8 DS841F2
PLL PERFORMANCE PLOTS
Test Conditions (unless otherwise specified): VD = 3.3 V; T
A
=25°C; C
L
=15pF; f
CLK_OUT
= 12.288 MHz;
f
CLK_IN
= 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz); AuxOutSrc[1:0] =11.
1 10 100 1,000 10,000
0.1
1
10
100
1,000
10,000
Input Jitter Frequency (Hz)
Max Input Jitter Level (usec)
1 Hz Bandwidth
128 Hz Bandwidth
1 10 100 1000 10000
-60
-50
-40
-30
-20
-10
0
10
Input Jitter Frequency (Hz)
Jitter Transfer (dB)
1 Hz Bandwidth
128 Hz Bandwidth
Figure 2. CLK_IN Sinusoidal Jitter Tolerance Figure 3. CLK_IN Sinusoidal Jitter Transfer
Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz). Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).
Figure 4. CLK_IN Random Jitter Rejection and Tolerance
0.01 0.1 1 10 100 1000
0.01
0.1
1
10
100
1000
Input Jitter Level (nsec)
Output Jitter Level (nsec)
1 Hz Bandwidth
128 Hz Bandwidth
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