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Fractional-N Clock Multiplier

Features

 Clock Multiplier / Jitter Reduction

– Generates a Low Jitter 6 - 75 MHz Clock

from a Jittery or Intermittent 50 Hz to 30

MHz Clock Source

 Highly Accurate PLL Multiplication Factor

– Maximum Error Less Than 1 PPM in High-

Resolution Mode

 One-Time Programmability

– Configurable Hardware Control Pins

– Configurable Auxiliary Output

 Flexible Sourcing of Reference Clock

– External Oscillator or Clock Source

– Supports Inexpensive Local Crystal

 Minimal Board Space Required

– No External Analog Loop-filter

Components

General Description

The CS2100-OTP is an extremely versatile system

clocking device that utilizes a programmable phase lock

loop. The CS2100-OTP is based on a hybrid analog-

digital PLL architecture comprised of a unique combina-

tion of a Delta-Sigma Fractional-N Frequency

Synthesizer and a Digital PLL. This architecture allows

for generation of a low-jitter clock relative to an external

noisy synchronization clock with frequencies as low as

50 Hz. The CS2100-OTP has many configuration op-

tions which are set once prior to runtime. At runtime

there are three hardware configuration pins available for

mode and feature selection.

The CS2100-OTP is available in a 10-pin MSOP pack-

age in Commercial (-10°C to +70°C) and Automotive

(-40°C to +85°C) grades. Customer development kits

are also available for custom device prototyping, small

production programming, and device evaluation.

Please see “Ordering Information” on page 26 for com-

plete details.

Hardware Configuration

Auxiliary

Output

6 to 75 MHz

PLL Output

Frequency Reference

3.3 V

Hardware

Control

8 MHz to 75 MHz

Low-Jitter Timing

Reference

Fractional-N

Frequency Synthesizer

Digital PLL &

Fractional N Logic

Output to Input

Clock Ratio

Timing Reference

PLL Output

Lock Indicator

50 Hz to 30 MHz

Frequency

Reference

MAY '10

DS841F2

CS2100-OTP

Summary of content (26 pages)

PAGE 1
CS2100-OTP Fractional-N Clock Multiplier Features General Description  Clock Multiplier / Jitter Reduction The CS2100-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL.
PAGE 2
CS2100-OTP TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS ......................................
PAGE 3
CS2100-OTP 9. PACKAGE DIMENSIONS .................................................................................................................... 25 THERMAL CHARACTERISTICS ......................................................................................................... 25 10. ORDERING INFORMATION .............................................................................................................. 26 11. REVISION HISTORY ..................................................................
PAGE 4
CS2100-OTP 1. PIN DESCRIPTION VD 1 10 M0 GND 2 9 M1 CLK_OUT 3 8 M2 AUX_OUT 4 7 XTI/REF_CLK CLK_IN 5 6 XTO Pin Name # Pin Description VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections. GND 2 Ground (Input) - Ground reference. CLK_OUT 3 PLL Clock Output (Output) - PLL clock output. AUX_OUT 4 Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks, or a status signal, depending on configuration.
PAGE 5
CS2100-OTP 2. TYPICAL CONNECTION DIAGRAM 0.1 µF 1 µF +3.3 V VD M2 System Microcontroller M1 M0 CS2100-OTP Frequency Reference CLK_IN 1 or 2 XTI/REF_CLK CLK_OUT To circuitry which requires a low-jitter clock AUX_OUT To other circuitry or Microcontroller XTO GND Low-Jitter Timing Reference REF_CLK 1 N.C. x XTO or Crystal XTI 2 XTO 40 pF 40 pF Figure 1.
PAGE 6
CS2100-OTP 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. (Note 1) Parameters Symbol Min Typ Max Units (Note 2) VD 3.1 3.3 3.5 V Commercial Grade Automotive Grade TAC TAD -10 -40 - +70 +85 °C °C DC Power Supply Ambient Operating Temperature (Power Applied) Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. 2.
PAGE 7
CS2100-OTP AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); TA = -40°C to +85°C (Automotive Grade); CL = 15 pF. Parameters Crystal Frequency Fundamental Mode XTAL Symbol Conditions Min Typ Max Units fXTAL RefClkDiv[1:0] = 10 RefClkDiv[1:0] = 01 RefClkDiv[1:0] = 00 RefClkDiv[1:0] = 10 RefClkDiv[1:0] = 01 RefClkDiv[1:0] = 00 8 16 32 - 18.75 37.5 50 MHz MHz MHz 8 16 32 - 18.75 37.
PAGE 8
CS2100-OTP PLL PERFORMANCE PLOTS Test Conditions (unless otherwise specified): VD = 3.3 V; TA = 25 °C; CL = 15 pF; fCLK_OUT = 12.288 MHz; fCLK_IN = 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz); AuxOutSrc[1:0] = 11. 10,000 10 1 Hz Bandwidth 128 Hz Bandwidth 1 Hz Bandwidth 128 Hz Bandwidth 0 -10 Jitter Transfer (dB) Max Input Jitter Level (usec) 1,000 100 10 -20 -30 -40 1 -50 0.
PAGE 9
CS2100-OTP 4. ARCHITECTURE OVERVIEW 4.1 Delta-Sigma Fractional-N Frequency Synthesizer The core of the CS2100 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolution for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to quickly tune to a new frequency. In very simplistic terms, the Fractional-N Frequency Synthesizer multiplies the Timing Reference Clock by the value of N to generate the PLL output clock.
PAGE 10
CS2100-OTP Delta-Sigma Fractional-N Frequency Synthesizer Timing Reference Clock Phase Comparator Internal Loop Filter Voltage Controlled Oscillator PLL Output Fractional-N Divider Delta-Sigma Modulator Digital PLL and Fractional-N Logic N Digital Filter Frequency Reference Clock Frequency Comparator for Frac-N Generation Output to Input Ratio for Hybrid mode Figure 6.
PAGE 11
CS2100-OTP 5. APPLICATIONS 5.1 One Time Programmability The one time programmable (OTP) circuitry in the CS2100-OTP allows for pre-configuration of the device prior to use in a system. There are two types of parameters that are used for device pre-configuration: modal and global. The modal parameters are features which, when grouped together, create a modal configuration set (see Figure 16 on page 20).
PAGE 12
CS2100-OTP example of how to determine the range of RefClk frequencies around 12 MHz to be used in order to achieve the lowest jitter PLL output at a frequency of 12.288 MHz is as follows: f L ≤ f RefClk ≤ f H where: CLK__OUT Jitter 180 *32/N f CLK__OUT Typical Base Band Jitter (psec) 31 f L = f CLK_OUT × ------ + 15kHz 32 = 12.288MHz × 0.96875 + 15kHz = 11.919MHz and 32 f H = f CLK_OUT × ------ – 15kHz 32 160 140 120 100 -15 kHz 80 +15 kHz 60 40 = 12.288MHz × 1 + 15kHz 20 -80 = 12.
PAGE 13
CS2100-OTP clock (SysClk). This allows the low-jitter timing reference clock to be used as the clock which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency reference clock through the Digital PLL. The allowable frequency range for CLK_IN is found in the “AC Electrical Characteristics” on page 7. 5.3.
PAGE 14
CS2100-OTP While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is achieved, the digital loop bandwidth will settle to the minimum value selected by the ClkIn_BW[2:0] parameter. Referenced Control Parameter Definition ClkIn_BW[2:0] .......................“Clock Input Bandwidth (ClkIn_BW[2:0])” on page 22 5.4 5.4.
PAGE 15
CS2100-OTP 5.4.2 Ratio Modifier (R-Mod) The Ratio Modifier is used to internally multiply/divide the currently addressed RUD (Ratio0-3 stored in the register space remain unchanged). The available options for R-Mod are summarized in Table 2 on page 15. R-Mod is enabled via the M2 pin in conjunction with the appropriate setting of the M2Config[2:0] global parameter (see Section 5.7.2 on page 18). RModSel[1:0] R Modifier 00 0.5 01 0.25 10 0.125 11 0.0625 Table 2.
PAGE 16
CS2100-OTP final calculation used to determine the output to input clock ratio. The effective ratio is then corrected for the internal dividers. The conceptual diagram in Figure 12 summarizes the features involved in the calculation of the ratio values used to generate the fractional-N value which controls the Frequency Synthesizer. The subscript ‘4’ indicates the modal parameters.
PAGE 17
CS2100-OTP 5.6 Auxiliary Output The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 14, to one of four signals: reference clock (RefClk), input clock (CLK_IN), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is controlled via the AuxOutSrc[1:0] modal parameter. If AUX_OUT is set to Lock, the AuxLockCfg global parameter is then used to control the output driver type and polarity of the LOCK signal (see section 6.3.1 on page 21).
PAGE 18
CS2100-OTP 5.7.2 M2 Mode Pin Functionality M2 usage is mapped to one of the optional special functions via the M2Config[2:0] global parameter. Depending on what M2 is mapped to, it will either act as an output enable/disable pin or override certain modal parameters. Figure 15 summarizes the available options and the following sections will describe each option in more detail.
PAGE 19
CS2100-OTP 5.8 Clock Output Stability Considerations 5.8.1 Output Switching The CS2100-OTP is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an output, changing the auxiliary output source between REF_CLK and CLK_OUT, and the automatic disabling of the output(s) during unlock will not cause a runt or partial clock period.
PAGE 20
CS2100-OTP 6. PARAMETER DESCRIPTIONS As mentioned in Section 5.1 on page 11, there are two different kinds of parameter configuration sets, Modal and Global. These configuration sets, shown in Figure 16, can be programmed in the field using the CDK2000 or preprogrammed at the factory. Please see “Programming Information” on page 24 for more details.
PAGE 21
CS2100-OTP 6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) Selects the source of the AUX_OUT signal. AuxOutSrc[1:0] Auxiliary Output Source 00 RefClk. 01 CLK_IN. 10 CLK_OUT. 11 PLL Lock Status Indicator. Application: “Auxiliary Output” on page 17 Note: When set to 11, the AuxLockCfg global parameter sets the polarity and driver type (“AUX PLL Lock Output Configuration (AuxLockCfg)” on page 21). 6.
PAGE 22
CS2100-OTP 6.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl) Defines the state of the PLL output during the PLL unlock condition. 6.3.4 ClkOutUnl Clock Output Enable Status 0 Clock outputs are driven ‘low’ when PLL is unlocked. 1 Clock outputs are always enabled (results in unpredictable output when PLL is unlocked). Application: “PLL Clock Output” on page 16 Low-Frequency Ratio Configuration (LFRatioCfg) Determines how to interpret the currently indexed 32-bit User Defined Ratio. 6.3.
PAGE 23
CS2100-OTP 7. CALCULATING THE USER DEFINED RATIO Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User Defined Ratio. This section is for those who would like to know more about how the User Defined Ratio is calculated and stored. Most calculators do not interpret the fixed point binary representation which the CS2100-OTP uses to define the output to input clock ratio (see Section 5.4.
PAGE 24
CS2100-OTP 8. PROGRAMMING INFORMATION Field programming of the CS2100-OTP is achieved using the hardware and software tools included with the CDK2000. The software tools can be downloaded from www.cirrus.com for evaluation prior to ordering a CDK. The CDK2000 is designed with built-in features to ease the process of programming small quantities of devices for prototype and small production builds.
PAGE 25
CS2100-OTP 9. PACKAGE DIMENSIONS 10L MSOP (3 mm BODY) PACKAGE DRAWING (Note 1) N D E11 c E A2 A ∝ e b A1 SIDE VIEW 1 2 3 END VIEW L SEATING PLANE L1 TOP VIEW DIM MIN INCHES NOM A A1 A2 b c D E E1 e L L1 -0 0.0295 0.0059 0.0031 ----0.0157 -- -----0.1181 BSC 0.1929 BSC 0.1181 BSC 0.0197 BSC 0.0236 0.0374 REF MAX 0.0433 0.0059 0.0374 0.0118 0.0091 ----0.0315 -- MIN MILLIMETERS NOM NOTE MAX -0 0.75 0.15 0.08 ----0.40 -- -----3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 0.60 0.95 REF 1.10 0.
PAGE 26
CS2100-OTP 10.ORDERING INFORMATION The CS2100-OTP is ordered as an un-programmed device. The CS2100-OTP can also be factory programmed for large quantity orders. Please see “Programming Information” on page 24 for more details.