Owner's manual
50 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23
Version 2.3
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
Figure 30. CM-2 RevF Schematic Page 7 of 7
HRESET#
GND
HEN#
GND
HRW
GND
HREQ#
GND
HACK#
GND
HDS#
GND
SSI_CLK
SSI_DOUT0
GND
SSI_DOUT1
GND
SSI_DOUT2
GND
SSI_DOUT3
GND
SSI_DIN0
GND
SSI_DIN1
GND
SSI_DIN2
GND
SSI_DIN3
GND
FS1
GND
MCLK_OUT
GND
MCLK_IN
GND
REFCLK_IN
UART_RXD
GND
UART_TXD
VCC_+3.3
UART_TX_OE
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
HDATA0
VCC_+3.3
HDATA1
VCC_+3.3
HDATA2
VCC_+3.3
HDATA3
HDATA4
VCC_+3.3
HDATA5
VCC_+3.3
HDATA6
VCC_+3.3
HDATA7
HRESET#
HADDR0
HEN#
HADDR1
HRW
HADDR2
HREQ#
HRESET#
HACK#
HACK#
HDS#
HDATA[0..7]
SSI_CLK
HADDR[0..3]
SSI_DOUT0
SSI_DOUT1
SSI_DOUT2
SSI_DOUT3
SSI_DIN0
SSI_DIN1
SSI_DIN2
SSI_DIN3
FS1
MCLK_OUT
MCLK_IN
REFCLK_IN
UART_RXD UART_TXD
UART_TX_OE
HADDR3
MUTE#
VCC_+5
VCC_+5
HRW
HDS#
HEN#
HREQ#
HDATA[0..7]
HADDR[0..3]
SSI_DOUT[0..3]
SSI_DIN[0..3]
HDATA0
SSI_DOUT[0..3]
HDATA1
SSI_DIN[0..3]
HDATA2
SSI_CLK
HDATA3
MCLK_OUT
HDATA4
FS1
HDATA5
UART_TXD
HDATA6
UART_RXD
HDATA7
MCLK_IN
HADDR0
REFCLK_IN
HADDR1
UART_TX_OE
HADDR2
VCC_+3.3
C33
0.1 uF
C34
0.1 uF
C35
0.1 uF
C36
0.1 uF
C37
0.1 uF
C38
0.1 uF
VCC_+5
C39
0.1 uF
AC Signal Return Path Caps
VCC_+3.3
Power Decoupling Caps
AUX_POWER0 AUX_POWER1
AUX_POWER2 AUX_POWER3
AUX_POWER0
AUX_POWER1
AUX_POWER2
AUX_POWER3
AUX_POWER[0..3]
AUX_POWER[0..3]
WATCHDOG
WATCHDOG
WATCHDOG
MUTE#
MUTE#
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
J3
CNM_CONN40
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
J1
CNM_CONN40
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
J4
CNM_CONN40
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
J2
CNM_CONN40
Note: Similar AC signal return path caps must be included on the motherboard near the connector.
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
VCC_+3.3
HRESET#
HEN#
HRW
HREQ#
HACK#
HDS#
SSI_CLK
SSI_DOUT0
SSI_DOUT1
SSI_DOUT2
SSI_DOUT3
SSI_DIN0
SSI_DIN1
SSI_DIN2
SSI_DIN3
FS1
MCLK_OUT
MCLK_IN
REFCLK_IN
UART_RXD UART_TXD
UART_TX_OE
HADDR3
MUTE#
VCC_+5
VCC_+5
HDATA0
HDATA1
HDATA2
HDATA3
HDATA4
HDATA5
HDATA6
HDATA7
HADDR0
HADDR1
HADDR2
AUX_POWER0 AUX_POWER1
AUX_POWER2 AUX_POWER3
WATCHDOG
1
M3
MOUNTING
1
M4
MOUNTING
1
M2
MOUNTING
1
M1
MOUNTING
R40
0 Ohm
R39
0 Ohm
These two mounting holes are located at the
"back" of the CM-2, near the main interface
connectors.
These two mounting holes are located near
the front panel of the CM-2.
C10
10 uF, X5R, 6.3 Volts
C11
10 uF, X5R, 6.3 Volts
C12
10 uF, X5R, 6.3 Volts
C13
10 uF, X5R, 6.3 Volts
C14
10 uF, X5R, 6.3 Volts
RSVD3 RSVD3
RSVD1
RSVD2
RSVD4
RSVD1
RSVD2
RSVD4
HADDR3
HADDR0
HADDR1
HADDR2
HDATA0
HDATA1
HDATA2
HDATA3
HDATA4
HDATA5
HDATA6
HDATA7
HEN#
HDS#
HACK#
HREQ#
UART_TX_OE
UART_TXD
UART_RXD
REFCLK_IN
GND
SSI_DOUT3
RSVD2
RSVD4
RSVD5
SSI_DIN0
SSI_DIN1
SSI_DIN2
SSI_DIN3
RSVD3
FS1
SSI_CLK
Note: Pull-ups/downs on SSI_DOUT[0..4] are located on the DSP schematic page.
MCLK_IN
These pullups/downs are used to assure a valid logic level if a signal is
tri-stated or not connected. In some situations, these may not be required.
C50
0.01 uF, 2KV
SHIELD
Place near the Ethernet connectors.
12
3
4
5
6
7
8
9
10
RN3
10K Ohm, 8x Array
12
3
4
5
6
7
8
9
10
RN4
10K Ohm, 8x Array
12
3
4
5
6
7
8
9
10
RN5
10K Ohm, 8x Array
12
3
4
5
6
7
8
9
10
RN6
10K Ohm, 8x Array
GND
GND
GND
GND
GND
VCC_+3.3
VCC_+3.3
HADDR3
RSVD[1..5]
RSVD[1..5]
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5