Owner's manual
CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
DS651UM23 ©Copyright 2005 Cirrus Logic, Inc. 47
Version 2.3
Figure 27. CM-2 RevF Schematic Page 4 of 7
VCXO_CTRL
1
MCLK_SEL
2
DBDA
3
DBCK
4
NC
5
NC
6
NC
7
DAO_MCLK
8
TEST
9
VDDD
10
HS3
11
NC
12
GND
13
DAO2_LRCLK
14
DAO1_DATA3
15
DAO1_DATA2/HS2
16
DAO1_DATA1/HS1
17
VDDIO
18
DAO1_DATA0/HS0
19
DAO1_SCLK
20
GND
21
DAO1_LRCLK
22
UART_TX_OE
23
VDDD
24
UART_TXD
25
UART_RXD
26
GND
27
NC
28
VDDIO
33
GND
36
EXT_WE#
38
VDDIO
44
GND
47
NC
50
NC
51
NC
52
NC
53
VDDD
54
SD_A12/EXT_A11
55
SD_A11/EXT_A10
56
GND
57
SD_A9/EXT_A9
58
SD_A8/EXT_A8
59
VDDIO
60
SD_A7/EXT_A7
61
SD_A6/EXT_A6
62
GND
63
SD_A5/EXT_A5
64
EXT_CS2#
65
VDDD
66
SD_A4/EXT_A4
67
SD_A3/EXT_A3
68
GND
69
SD_A2/EXT_A2
70
SD_A1/EXT_A1
71
SD_A0/EXT_A0
72
VDDIO
73
SD_A10/EXT_A12
74
SD_A14/EXT_A13
75
GND
76
SD_A13/EXT_A14
77
NC
78
NC
79
NC
80
NC
81
EXT_A15
82
VDDD
83
EXT_A16
84
EXT_A17
85
GND
86
EXT_A18
87
EXT_A19
88
EXT_OE#
89
EXT_CS1#
90
VDDIO
91
MUTE#
92
RESET#
93
GND
94
WATCHDOG_OUT
95
IOWAIT
96
REFCLK_IN
97
VDDD
98
GPIO0
99
GPIO1
100
GND
101
HACK#
102
HDS#
103
HEN#
104
HADDR3
105
HADDR2
106
HR/W#
107
GPIO2
108
HADDR1
109
HADDR0
110
HDATA7
111
HDATA6
112
VDDIO
113
HDATA5
114
HDATA4
115
GND
116
HDATA3
117
HDATA2
118
VDDD
119
HDATA1
120
HDATA0
121
GND
122
XTAL_OUT
123
XTI
125
XTO
124
GND_A
126
FILT2
127
FILT1
128
VDD_A
129
VDDD
130
DAI1_DATA3
131
DAI1_DATA2
132
GND
133
DAI1_DATA1
134
DAI1_DATA0
135
VDDIO
136
DAI1_SCLK
137
DAI1_LRCLK
138
GND
139
HREQ#
140
NC
141
NC
142
IRQ1
143
IRQ2
144
SD_D7/EXT_D15
29
SD_D6/EXT_D14
30
SD_D5/EXT_D13
31
SD_D4/EXT_D12
32
SD_D3/EXT_D11
34
SD_D2/EXT_D10
35
SD_D1/EXT_D9
37
SD_D0/EXT_D8
39
SD_D15/EXT_D7
40
SD_D14/EXT_D6
41
SD_D13/EXT_D5
42
SD_D12/EXT_D4
43
SD_D11/EXT_D3
45
SD_D10/EXT_D2
46
SD_D9/EXT_D1
48
SD_D8/EXT_D0
49
U6
CS18101
VCC_+1.8 VCC_+3.3
HRESET_BUF#
OE#
WE#
FLASH_CS#
MAC_CS#
IOWAIT
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
UART_TXD
UART_RXD
UART_TX_OE
HDATA0
HDATA1
HDATA2
HDATA3
HDATA4
HDATA5
HDATA6
HDATA7
HADDR0
HADDR1
HADDR2
HADDR3
HRW
HDS#
HREQ#
HACK#
HEN#
MCLK_INTERNAL
FS1
SSI_CLK
SSI_DIN0
SSI_DIN1
SSI_DIN2
SSI_DIN3
SSI_DOUT0
SSI_DOUT1
SSI_DOUT2
SSI_DOUT3
RSVD1
RSVD2
RSVD4
RSVD3
VCXO_CTRL
MAC_IRQ0
MAC_IRQ1
MCLK_SEL
DATA[0..15]
ADDR[0..19]
HRESET_BUF#
OE#
WE#
FLASH_CS#
MAC_CS#
IOWAIT
C41
22 pF
C40
22 pF
SSI_DOUT[0..3]
SSI_DIN[0..3]
HADDR[0..3]
HDATA[0..7]
DATA[0..15]
ADDR[0..19]
UART_TX_OE
UART_RXD
UART_TXD
HRW
HDS#
HEN#
HREQ#
HACK#
HADDR[0..3]
HDATA[0..7]
MCLK_INTERNAL
FS1
SSI_CLK
SSI_DOUT[0..3]
SSI_DIN[0..3]
MCLK_SEL
VCXO_CTRL
MAC_IRQ0
MAC_IRQ1
GPIO0
GPIO1
GPIO[0..1]
GPIO[0..1]
REFCLK_IN
WATCHDOG
MUTE#
REFCLK_IN
WATCHDOG
MUTE#
VCC_+3.3
VCC_+1.8
VCC_+1.8
C24
0.1 uF
FB1
FBEAD, 68 Ohm @ 100 MHz
C4
10 uF, X5R, 6.3 Volts
C5
10 uF, X5R, 6.3 Volts
VCC_DSPA
R13
R14
3.3K Ohm
VCC_+3.3
VCC_+3.3
GND
DEBUG_CLK
DEBUG_DATA
Debug Port
RSVD1
SSI_DOUT0
SSI_DOUT1
SSI_DOUT2
HS0 - Down
HS1 - Up
HS2 - Down
HS3 - Down
1
2
3
45
6
7
8
CN3
0.1 uF, 4x Array
1
2
3
45
6
7
8
CN2
0.1 uF, 4x Array
VCC_+3.3
VCC_+1.8
1
2
3
45
6
7
8
CN5
0.1 uF, 4x Array
1
2
3
45
6
7
8
CN4
0.1 uF, 4x Array
VCC_+1.8
1
2
3
45
6
7
8
CN1
0.1 uF, 4x Array
GND
C43
1000 pF, COG
R41
5.90K Ohm
C42
2.2 uF, X7R, 1206
CLK_25
CLK_25
1 2
Y1
25 MHz
VCC_+3.3
SSI_CLK_J
C44
0.1 uF
R45
24.9 Ohm, 1%
VCC_+3.3
1
2
3
45
6
7
8
CN12
0.1 uF, 4x Array
R53
R54
24.9 Ohm, 1%
DAO1_LRCLK
SSI_CLK_J
R43
R47
R49
R51
3.3K Ohm
R42
R46
R48
R50
3.3K Ohm
Default Boot Mode:
These pullups and pulldowns are used
to set the boot mode of the DSP. The
appropriate resistor is installed to select
the boot mode.
1
2
3
4
JP1
CON4
R55
1 MegOhm
RSVD[1..5]
RSVD[1..5]
RSVD[1..5]
RSVD5
9
10
8
U10C
74LVC32
GND
A/B
1
1A
2
1B
3
1Y
4
2A
5
2B
6
2Y
7
GND
8
3Y
9
3B
10
3A
11
4Y
12
4B
13
4A
14
G
15
VCC
16
U11
74LVC157
C53
0.1 uF
VCC_+3.3
VCC_+3.3
C52
0.1 uF
D1
1N4148W
GND
GND
GND
GND
GND
GND
GND
DAO2_LRCLK
DAO1_LRCLK
DAO2_LRCLK
R57
10K Ohm
R56
3.3K Ohm
DAO1_LRCLK