CS1810xx, CS4961xx, & CM-2 Digital Audio Networking Processor CobraNet ™ Silicon Series CS18100x, CS18101x, CS18102x, and CM-2 CS49610x, CS49611x, and CS49612x Hardware User’s Manual Version 2.3 Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. ©Copyright 2005 Cirrus Logic, Inc. http://www.cirrus.
CobraNet Hardware User’s Manual Table of Contents Table of Contents List of Figures......................................................................................................................................... 4 1.0 .Introduction ..................................................................................................................................... 5 2.0 Features .........................................................................................................................
CobraNet Hardware User’s Manual Table of Contents 7.4.3 Data................................................................................................................... 32 7.4.3.1. Region length ........................................................................................ 32 7.4.3.2. Writable Region ..................................................................................... 32 7.4.3.3. Translation Complete .........................................................................
CobraNet Hardware User’s Manual List of Figures List of Figures Figure 1. CobraNet Data Services ......................................................................................................... 5 Figure 2. CobraNet Interface Hardware Block Diagram......................................................................... 8 Figure 3. Audio Clock Sub-system....................................................................................................... 17 Figure 4.
CobraNet Hardware User’s Manual Introduction 1.0 Introduction This document is intended to help hardware designers integrate the CobraNetTM interface into an audio system design. It covers the CS18100x, CS18101x, CS18102x, CS49610x, CS49611x, and CS49612x members of the CobraNetTM Silicon Series of devices, where “x” is the ROM version (ROM ID). This document also describes the CM-2 module with schematics, mechanical drawings, etc.
CobraNet Hardware User’s Manual Features 2.0 Features 2.1 CobraNet • Real-time Digital Audio Distribution via Ethernet • No Overall Limit on Network Channel Capacity • Fully IEEE 802.3 Ethernet Standards Compliant • Fiber optic and gigabit Ethernet variants are fully supported. • Ethernet infrastructure can be used simultaneously for audio and data communications.
CobraNet Hardware User’s Manual Features 2.3 Host Interface • 8-bit Data, 4-bit Address • Virtual 24-bit Addressing with 32-bit Data • Polled, Interrupt, and DMA Modes of Operation • Configure and Monitor CobraNet Interface • Transmit or Receive Ethernet Packets at Near-100-Mbit Wire Speed 2.4 Asynchronous Serial Interface • Full-duplex Capable • 8-bit Data Format • Supports all Standard Baud Rates 2.
CobraNet Hardware User’s Manual Hardware 3.0 Hardware Figure 2 shows a high-level view of the CobraNet CM-2 interface hardware architecture. Clock VCXO Clock CobraNet CM-2 Module Flash Memory Control Audio Serial Host CS1810xx/ CS4961xx Ethernet Controller Ethernet Magnetics Figure 2. CobraNet Interface Hardware Block Diagram Flash memory holds the CobraNet firmware and management interface variable settings. The CS1810xx or CS4961xx network processor is the heart of the CobraNet interface.
CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.
CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.1 CS1810xx & CS4961xx Package Pinouts 4.1.1 CS1810xx/CS4961xx Pinout Table 1 lists the pinout for the 144-pin LQFP CS1810xx/CS4961xx device. The interfaces for these signals are expanded in the following sections. Table 1.
CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.1.2 CM-2 Connector Pinout Table 1 lists the pinout for the four pinout connectors on the CM-2 board (J1-J4). The interfaces for these signals are expanded following the table. Table 2. CM-2 Pin Assignments Conn. Pin # Pin Name Conn. Pin # B8 Pin Name GND Conn. J3/J4 Pin # A15 Pin Name J1/J2 A1 UART_RXD J1/J2 DAI1_DATA3 J1/J2 A2 UART_TX_OE J1/J2 B9 VCC_+3.
CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.2 Signal Descriptions 4.2.1 Host Port Signals The host port is used to manage and monitor the CobraNet interface. Electrical operation and protocol is detailed in the "Host Management Interface (HMI)" on page 23 of this Manual. The host port can operate in two modes in order to accomodate Motorola® or Intel® style interfaces. The default mode is Motorola. Intel mode is set via a firmware modification.
CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.2.3 Synchronous Serial (Audio) Signals The synchronous serial interfaces are used to bring digital audio into and out of the system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing and format is described in "Digital Audio Interface" on page 19. Signal Description CM-2 Pin # Direction CS1810xx/ CS4961xx Pin # Notes Synchronous serial bit clock.
CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.2.5 Miscellaneous Signals Signal Description Direction CM-2 Pin # CS1810xx/ CS4961xx Pin # HRESET Reset In J1:A18 93 System reset (active low). 10 ns max rise time. 1 ms min assertion time. Notes WATCHDOG Watch Dog Out J3:A17 95 Toggles at 750 Hz nominal rate to indicate proper operation. Period duration in excess of 200 ms indicates hardware or software failure has occurred and the interface should be reset.
CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.2.7 System Signals Use these CS1810xx/CS4961xx signals stricktly in the manner described in CM-2 Schematics (Section 9.2 on page 44). Each signal is briefly described below. Signal VCXO_CTRL MCLK_SEL DBDA, DBCK TEST Description CS1810xx/CS4961xx Pin # A Delta-sigma DAC Output for Controlling the On-board VCXO 1 Control Signal for Selecting MCLK Sources 2 I2C Debugger Interface Used for testing during manufacturing.
CobraNet Hardware User’s Manual Pinout and Signal Descriptions 4.3 Characteristics and Specifications 4.3.1 Absolute Maximum Ratings Parameter DC power supplies: Core supply PLL supply I/O supply |VDDA – VDD| Input current, any pin except supplies Input voltage on FILT1, FILT2 Input voltage on I/O pins Storage temperature Symbol VDD VDDA VDDIO Min –0.3 –0.3 –0.3 - Iin Vfilt Vinio Tstg Max 2.0 2.0 5.0 0.3 +/- 10 2.0 5.
CobraNet Hardware User’s Manual Synchronization 5.0 Synchronization Figure 3 shows clock related circuits for the CS1810xx/CS4961xx and board design (CM-2). This circuitry allows the synchronization modes documented below to be achieved. Modes are distinguished by different settings of the multiplexors and software elements. MCLK_OUT VCXO 24.
CobraNet Hardware User’s Manual Synchronization The following synchronization modes are further described below: • "Internal Mode" on page 18 • "External Word Clock Mode" on page 18 • "External Master Clock Mode" on page 18 5.1.1 Internal Mode All CobraNet clocks are derived from the onboard VCXO. The master clock generated by the VCXO is available to external circuits via the master clock output. Conductor—The VCXO is “parked” according to the syncClockTrim setting.
CobraNet Hardware User’s Manual Digital Audio Interface 6.0 Digital Audio Interface The CS18101x/CS49611x, CS18102x/CS49612x, and CM-2 support four bi-directional synchronous serial interfaces. The CS18100x & CS49610x support one bi-directional synchronous serial interface. All interfaces operate in master mode with DAO1_SCLK as the bit clock and FS1 as the frame clock. A sample period worth of synchronous serial data includes two (or four) audio channels.
CobraNet Hardware User’s Manual Digital Audio Interface Although data is always transmitted and received with a 32-bit resolution by the synchronous serial ports, the resolution of the data transferred to/from the Ethernet may be less. Incoming audio data is truncated to the selected resolution. Unused least significant bits on outgoing data is zero filled. 6.1 Digital Audio Interface Timing 0 – 5ns MCLK_OUT DAO1_SCLK FS1 0 – 10ns Figure 6.
CobraNet Hardware User’s Manual Digital Audio Interface 6.1.1 Normal Mode Data Timing DAI1_SCLK FS1 DAI1_DATAx DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 4 3 2 1 0 Unused 23 8 7 6 5 4 3 2 1 0 Unused 23 Figure 8.
CobraNet Hardware User’s Manual Digital Audio Interface 6.1.3 Standard Mode Data Timing DAI1_SCLK FS1 DAI1_DATAx DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 6 5 8 7 6 4 3 2 5 4 3 2 1 0 Unused 23 1 0 Unused 23 Figure 12.
CobraNet Hardware User’s Manual Host Management Interface (HMI) 7.0 Host Management Interface (HMI) 7.1 Hardware The host port is 8 bits wide with 4 bits of addressing. Ten of the 16 addressable registers are implemented. The upper two registers can be used to configure and retrieve the status on the host port hardware. However, only the first 8 are essential for normal HMI communications.
CobraNet Hardware User’s Manual Host Management Interface (HMI) HREQ may be wired to a host interrupt or DMA request input. HREQ is used to signal the host that data is available (read case, logic 0) or space is available in the host port data channel (write case, logic 1). The read and write case are distinguished by the HMI based on the preceding message. Identify, Goto Translation (read), Goto Packet (read) and Goto Counters cause HREQ to represent read status.
CobraNet Hardware User’s Manual Host Management Interface (HMI) HADDR[3:0] t m as t m ah HDATA[7:0] HEN M SP LSP t m dd t m rw su HRW t m dhr t m cdr t m dis t m rpw t m rw hld t m rdtw t m rd HDS t m rwirqh HREQ Figure 14. Host Port Read Cycle Timing - Motorola Mode H A D D R [3 :0 ] t m as H D A T A [7 :0 ] t m ah LSP t m d su MSP t m dhw HEN t m cdw t m r w h ld t m wpw HRW t m rw su t mwd t m w trd HDS t m rw irq l HREQ Figure 15.
CobraNet Hardware User’s Manual Host Management Interface (HMI) 7.
CobraNet Hardware User’s Manual Host Management Interface (HMI) H A D D R [3 :0 ] t iah H D A T A [7 :0 ] LSP t ias t id d HCS MSP t id hr t icdr t idis HW R t irp w t ird t irdtw HRD t ird irqh HREQ Figure 16. Parallal Control Port - Intel Mode Read Cycle H A D D R [3:0] t iah H DATA[7:0] LSP t ias MSP t idhw HCS t icdw HRD t idsu t iw pw t iw d t iw trd HW R t iwrbsyl HREQ Figure 17. Parallel Control Port - Intel Mode Write Cycle DS651UM23 Version 2.
CobraNet Hardware User’s Manual Host Management Interface (HMI) 7.4 Protocol and Messages The message conduit is used to issue commands to the CS1810xx/CS4961xx and retrieve HMI status. The data conduit is used to transfer data dependent on the HMI state as determined by commands issued by the host via the message conduit. 7.4.1 Messages Messages are used to efficiently invoke action in the CS1810xx/CS4961xx. To send a message, the host optionally writes to the A, B, and C registers.
CobraNet Hardware User’s Manual Host Management Interface (HMI) 7.4.1.1. Translate Address Translate Address does not actually update the address pointers but initiates the processing required to eventually move them. The host can accomplish other tasks, including HMI Reads and Writes while the address translation is being processed. A logical description of Translate Address is given below. A contextual use of the Translate Address operation is shown in the reference implementations.
CobraNet Hardware User’s Manual Host Management Interface (HMI) 7.4.1.5. Packet Received Sets bridgeRxPkt = bridgeRxReady thus acknowledging receipt of the packet in bridgeRxPktBuffer. void PacketReceive( void ) { int msgack = MSG_D; MSG_C = MOP_PACKET_RECEIVE; MSG_D = CVR_MULTIPLEX_OP; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); } 7.4.1.6. Packet Transmit Sets bridgeTxPkt = bridgeTxPktDone+1 thus initiating transmission of the contents of bridgeTxPktBuffer.
CobraNet Hardware User’s Manual Host Management Interface (HMI) 7.4.2 Status HMI status can always be retrieved by reading the message conduit. Status is updated in a pipelined manner whenever the Message D register is read. Reading the message conduit gives the current status as of the last time the conduit was read. Bitfields in the HMI Status Register are outlined in Table 5 below. Refer also to "HMI Definitions" on page 33 and "HMI Access Code" on page 34.
CobraNet Hardware User’s Manual Host Management Interface (HMI) 7.4.3 Data Before accessing data, address setup must be performed. Address setup consists of issuing a Translate Address request, waiting for the request to complete, then issuing a Goto Translation. Pipelining requires that a “garbage read” be performed following an address change. The second word read contains the data for the address requested. No similar pipelining issue exists with respect to write operations. 7.4.3.1.
CobraNet Hardware User’s Manual HMI Reference Code 8.0 HMI Reference Code The following C code provides examples in using HMI messages, HMI status, and the HMI memory map. 8.1 HMI Definitions /*======================================================================== ** hmi.h ** CobraNet Host Management Interface example code ** Definitions **-----------------------------------------------------------------------** $Header$ ** Copyright (c) 2004, Peak Audio, a division of Cirrus Logic, Inc.
CobraNet Hardware User’s Manual HMI Reference Code 8.2 HMI Access Code /*======================================================================== ** hmi.c ** CobraNet Host Management Interface example code ** Simple edition **-----------------------------------------------------------------------** $Header$ ** Copyright (c) 2004, Peak Audio, a division of Cirrus Logic, Inc. **========================================================================*/ #include "hmi.
CobraNet Hardware User’s Manual HMI Reference Code while( !( ReadRegister( MSG_D ) & ( 1 << MSG_TRANSLATION_BO ) ) ); /* goto translation */ WriteRegister( MSG_C, MOP_GOTO_TRANSLATION_READ ); SendMessage( CVR_MULTIPLEX_OP ); /* "garbage" read clears data pipeline */ ReadRegister( DATA_D ); /* maintain local pointers */ PeekPointer = PokePointer = address; PeekLimit = PokeLimit = PeekPointer + ReadRegister( MSG_C ) + ( ReadRegister( MSG_B ) << 8 ); /* read-only region addressed */ if( !( ReadRegister( MSG_A
CobraNet Hardware User’s Manual HMI Reference Code 8.3 CM-1, CM-2 Auto-detection The following function is useful for systems that support both the CM-1 and CM-2 or where a CobraNet interface is an optional add-in. Detect() returns 0 if no CobraNet interface module is detected, 1 for CM-1 and 2 for CM-2.
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics 9.0 Mechanical Drawings and Schematics The section contains detailed drawings of the CM-2 board and CS1810xx/CS4961xx device package design.
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics CM-2 Mechanical Drawings NOT TO SCALE 9.1 Figure 18. CM-2 Module Assembly Drawing, Top 38 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.
NOT TO SCALE CobraNet Hardware User’s Manual Mechanical Drawings and Schematics Figure 19. CM-2 Module Assembly Drawing, Bottom DS651UM23 Version 2.3 ©Copyright 2005 Cirrus Logic, Inc.
©Copyright 2005 Cirrus Logic, Inc. NOT TO SCALE 2x Mounting holes for front faceplate. 0.3 3.500 General PCB dimensions 2.86 Component Side = J1 Bottom Side = J2 A20 A20 A1 Viewed from component side up. B20 B1 B20 B1 Component Side = J3 Bottom Side = J4 0.175 0.175 4x 0.16 Hole, 0.3 pads 3.500 40 A1 2x Mounting holes for PCB standoffs CobraNet Hardware User’s Manual Mechanical Drawings and Schematics Figure 20. General PCB Dimensions DS651UM23 Version 2.
NOT TO SCALE 0.340 This distance accounts for the thickness of the faceplate CobraNet Hardware User’s Manual Mechanical Drawings and Schematics Figure 21. Example Configuration, Side View DS651UM23 Version 2.3 ©Copyright 2005 Cirrus Logic, Inc.
©Copyright 2005 Cirrus Logic, Inc. 2x, Hole Diameter 0.160 1.343 1.333 NOT TO SCALE 0.300 0.431 0.421 0.125 dia, 2x 0.175 0.550 0.680 0.700 Faceplate Dimensions Faceplate material is 20 guage, 0.037" thick Chrome plating on faceplate 3.500 0.175 1.000 max, 0.9 typ. 0.340 0.800 0.810 42 1.000 0.490 Note: Mechanical dimensions for the CM-2 and CM-1 Rev F are identical. There are differences with earlier versions of the CM-1, however.
3.343 CobraNet Hardware User’s Manual Mechanical Drawings and Schematics Component Side Up 1.576 1.925 J3 8x 0.047 Alignment holes 0.208 0.039 NOT TO SCALE 0.157 J1 Connector Detail Figure 23. Connector Detail DS651UM23 Version 2.3 ©Copyright 2005 Cirrus Logic, Inc.
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics 9.2 CM-2 Schematics connector connector.sch core core.sch HRESET# HRESET# HRESET# HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# HEN# HRW HDS# HADDR[0..3] HDATA[0..
VCXO_CTRL RSVD[1..5] REFCLK_IN WATCHDOG MUTE# GPIO[0..1] FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] UART_TX_OE UART_TXD UART_RXD HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# R12 3.3K Ohm CLK_25 VCXO_CTRL MCLK_SEL MCLK_INTERNAL RSVD[1..5] REFCLK_IN WATCHDOG MUTE# GPIO[0..1] FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] UART_TX_OE UART_TXD UART_RXD HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# C19 0.1 uF CLK_25 AB2 C2 D2 A1 B1 C1 D1 OUT OUT VCC VCC VCC C21 0.1 uF VCC_+3.3 24.
ADDR[0..19] HRESET_BUF# HRESET_BUF# ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 10 12 9 16 17 48 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25 NC D15/A-1 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CE# WE# OE# BYTE# NC/VPP NC/WP# NC/RY/BY# C23 0.1 uF VCC_+3.3 RESET# NC/A19 NC/A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 GND ADDR[0..19] VCC GND 27 ©Copyright 2005 Cirrus Logic, Inc.
8 6 8 1 VCC_+3.3 1 2 7 2 CLK_25 CN12 0.1 uF, 4x Array CN1 0.1 uF, 4x Array 8 VCC_+3.3 1 C40 22 pF CLK_25 ADDR[0..19] DATA[0..15] IOWAIT 1 ADDR[0..19] DATA[0..15] CN3 0.1 uF, 4x Array CN2 0.1 uF, 4x Array R55 1 MegOhm 25 MHz Y1 2 24.9 Ohm, 1% R45 8 4 7 6 1 3 6 3 2 7 2 5 4 5 4 7 8 VCC_+3.3 1 6 C42 2.
MAC_CS# OE# DATA[0..15] ADDR[0..19] MAC_CS# OE# 74LVC32 U10A DATA[0..15] ADDR[0..19] IOWAIT WE# MAC_IRQ0 HRESET_BUF# 2 1 3 8 1 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 VCC_+3.3 VCC_+3.
OE# MAC_CS# DATA[0..15] ADDR[0..19] 13 OE# 74LVC32 U10D DATA[0..15] ADDR[0..19] IOWAIT WE# MAC_IRQ1 HRESET_BUF# 12 MAC_CS# 11 8 1 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 VCC_+3.3 VCC_+3.
RSVD[1..5] WATCHDOG MUTE# AUX_POWER[0..3] SSI_CLK MCLK_IN MCLK_OUT FS1 REFCLK_IN UART_TX_OE UART_TXD UART_RXD SSI_DIN[0..3] SSI_DOUT[0..3] HADDR[0..3] RSVD[1..5] AUX_POWER[0..3] SSI_DIN[0..3] SSI_DOUT[0..3] HADDR[0..3] HDATA[0..
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics 9.3 CS1810xx/CS4961xx Package E E1 D D1 Notes: 1. Controlling dimension is millimeter. 2. Dimensioning and tolerancing per ASME Y14.5M-1994. e b SEATING PLANE ddd M B B L1 θ A A1 L Figure 31. 144-Pin LQFP Package Drawing MILLIMETERS INCHES DIM A MIN NOM MAX MIN NOM MAX --- --- 1.60 --- --- .063” A1 0.05 --- 0.15 .002” --- .006” b 0.17 0.22 0.27 .007” .009” .011” D 22.00 BSC .866” D1 20.00 BSC .
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics 9.4 Temperature Specifications • Thermal Coefficient (junction-to-ambient): θja - 38° C / Watt • Ambient Temperature Range: 0-70 deg C • Junction Temperature Range: 0-125 deg C 52 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.
CobraNet Hardware User’s Manual Ordering Information 10.0 Ordering Information 10.
CobraNet Hardware User’s Manual Ordering Information Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied).
