Owner manual

CS1630/31
36 DS954F3
6.17 Configuration 12 (Config12) Address 44
6.18 PU Coefficient (PID)
Address 45
PID sets the maximum coefficient for the second stage PU integrator. The register value is an unsigned integer
in the range of 0value255.
6.19 Maximum Switching Frequency (TTFREQ) Address 46
TTFREQ sets the minimum switching period (maximum switching frequency) for the second stage TT (see
"Maximum TT (TTMAX) – Address 38" on page 33). The register value is an unsigned integer in the range of
0value255. The minimum TTFREQ switching period is determined by:
The switching period for TT can be configured from 0ns to 51s.
76543210
TIMEOUT1 TIMEOUT0 S2CONFIG DITATT1 DITATT0 - - -
Number Name Description
[7:6] TIMEOUT[1:0]
Sets the T2 time-out limit to ensure a minimum switching frequency for each
channel.
00 = 45ms
01 = 70.6ms
10 = 96.2ms
11 = 121.8ms
[5] S2CONFIG
Configures second stage for flyback or buck/tapped buck.
0 = Enables second stage for buck/tapped buck topology
1 = Enables second stage for flyback topology
[4:3] DITATT[1:0]
Configures the dither attenuation by right shifting the dither value on a selected
channel for dithering reduction. The nominal dither level (set using bits DIT-
LEVEL[1:0]) is attenuated by the amount configured by bits DITATT[1:0] on the
channel set using bit DITCHAN.
00 = No attenuation
01 = 50% attenuation
10 = 25% attenuation
11 = 12.5% attenuation
[2:0] - Reserved
76543210
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
76543210
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
TTFREQ[7:0] 4 50ns