CS1630 CS1631 2-Channel TRIAC Dimmable LED Driver IC Features Overview • Best-in-class Dimmer Compatibility - Leading-edge (TRIAC) Dimmers - Trailing-edge Dimmers - Digital Dimmers (with Integrated Power Supply) • Correlated Color Temperature (CCT) Control System • Up to 85% Efficiency • Flicker-free Dimming • Programmable Dimming Profile - Constant CCT Dimming - Black Body Line Dimming • 0% Minimum Dimming Level • Temperature Compensated LED Current • End-of-line Programming Using Power Line Calibration
CS1630/31 TABLE OF CONTENTS 1.INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 3.2 3.3 3.4 3.
CS1630/31 6.ONE-TIME PROGRAMMABLE (OTP) REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27 6.28 6.29 6.30 6.31 6.32 6.33 6.34 6.35 6.36 6.37 6.38 6.39 6.40 6.41 6.42 6.43 6.44 6.45 6.46 6.47 6.48 6.49 6.50 6.51 6.52 6.53 Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CS1630/31 1.
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CS1630/31 3. CHARACTERISTICS AND SPECIFICATIONS 3.1 Electrical Characteristics Typical characteristics conditions: • TA = 25ºC, VDD = 12V, GND = 0V • All voltages are measured with respect to GND. • Unless otherwise specified, all currents are positive when flowing into the IC.
CS1630/31 Parameter Condition Symbol Min Typ Max Unit Minimum Switching Frequency tFB(Min) - 625 - Hz Maximum Switching Frequency tFB(Max) - 200 - kHz Second Stage Pulse Width Modulator Second Stage Gate Driver Output Source Resistance VDD = 12V - 24 - Output Sink Resistance VDD = 12V - 11 - Rise Time (Note 5) CL = 0.25nF - - 30 ns Fall Time (Note 5) CL = 0.25nF - - 20 ns Second Stage Protection Overcurrent Protection (OCP) VOCP(th) - 1.
CS1630/31 3.2 I2C™ Port Switching Characteristics Test conditions (unless otherwise specified): • Inputs: Logic 0 = GND = 0V, Logic 1 = 3.3V. • The CS1630/31 control port only supports I2C slave functionality. • It is recommended that a 2.2k pull-up resistor be placed from the SDA pin to VDD.
CS1630/31 3.3 Power Line Calibration Characteristics Typical characteristics conditions: • TA = 25ºC, VDD = 12V, GND = 0V • All voltages are measured with respect to GND. • Unless otherwise specified, all current is positive when flowing into the IC. Parameter Input Line Frequency Input Voltage CS1630 CS1631 Dual-bit 00 (“00”) Dual-bit 01 (“01”) Dual-bit 10 (“10”) Dual-bit 11 (“11”) Special Character (SC) Notes: 6. 7.
CS1630/31 3.4 Thermal Resistance Symbol Parameter Value Unit JA Junction-to-ambient Thermal Impedance 2 Layer PCB 4 Layer PCB 84 47 °C/W °C/W JC Junction-to-case Thermal Impedance 2 Layer PCB 4 Layer PCB 39 31 °C/W °C/W 3.5 Absolute Maximum Ratings Characteristics conditions: All voltages are measured with respect to GND. Pin Symbol 14 VDD Parameter IC Supply Voltage Value Unit 18.5 V 1, 2, 5, 6, 7, 9, 10, 11, 15, 16 Analog Input Maximum Voltage -0.5 to (VDD+0.
CS1630/31 4. TYPICAL PERFORMANCE PLOTS 3 12 10 8 IDD (mA) UVLO Hysteresis 2 6 4 1 2 0 0 -50 0 50 100 -2 150 0 2 4 6 Temperature (°C) 8 10 12 14 16 18 20 VDD (V) Figure 4. Supply Current vs. Voltage Figure 3. UVLO Characteristics 10 20 19.5 VZ (V) VDD (V) 9 Turn On 19 8 18.5 Turn Off 7 -50 0 50 100 18 150 -50 0 50 100 150 Temperature (°C) Temperature (C°) Figure 6. Zener Voltage vs. Temperature Figure 5. Turn-on/off Threshold Voltage vs. Temperature 0.
CS1630/31 5. GENERAL DESCRIPTION 5.1 Overview The CS1630 and CS1631 are high-performance offline AC/DC LED drivers for dimmable and high color rendering index (CRI) LED replacement lamps and luminaires. They feature Cirrus Logic’s proprietary digital dimmer compatibility control technology and digital correlated color temperature (CCT) control system that enables two-channel LED color mixing.
CS1630/31 waveform. The information from the probe event is used to maintain proper operation with the dimmer circuitry. Red and amber LEDs are necessary components in color-mixing applications when providing warm white or other CCTs. When mixing colors, red and amber LEDs are the most temperature sensitive, so they cause a large variation in temperature.
CS1630/31 3 2 3 2 2 2 GAIN DTR= P30 T + P20 T + P10 T + P03 D + P02 D + P01 D + P21 T D + P12 T D + P11 T D + P00 [Eq.1] where, T = the measured normalized temperature and is 0 T 1.0 D = the normalized dim value and is 0 D 1.0 GAINDTR = gain of the channel based on the temperature measurement and the dim value: 3 2 [Eq.2] GAIN DR = Q3 D + Q2 D + Q1 D + Q0 where, D = the normalized dim value and is 0 D 1.
CS1630/31 5.6.2 Output BSTOUT Sense & Input IAC Sense Resistor RIAC sets current IAC and is derived from Equation 5: A current proportional to boost output voltage VBST is supplied to the IC on pin BSTOUT and is used as a feedback control signal (see Figure 12). The ADC is used to measure the magnitude of current I BSTOUT through resistor R BST. The magnitude of current I BSTOUT is then compared to an internal reference current I ref of 133A. R8 RB S T R9 Iref BSTOUT 15k ADC Figure 12.
CS1630/31 The CS1630/31 provides active clamp circuitry on the CLAMP pin, as shown in Figure 14. VB S T Figure 15 illustrates a quasi-resonant configured for two-channel parallel output. flyback T1 VBST LED2+ R15 D10 Z2 C11 VDD R10 C9 D7 Z3 LED2- D9 ICLA MP D11 V CC _ Q CLAMP S1 Q3 3 C8 VB E CS1630 /31 FBAUX FBSENSE Clamp Overpower Protection The CS1630/31 clamp overpower protection (COP) control logic continuously monitors the turn-on time of the clamp circuit.
CS1630/31 The buck stage is controlled by measuring current in the buck inductor and voltage on the auxiliary winding. Quasi-resonant operation is achieved by detecting buck inductor demagnetization using an auxiliary winding. The digital control algorithm rejects line-frequency ripple created on the second stage input by the front-end boost stage, resulting in the highest possible LED efficiency and long LED life. The tapped buck stage operates similar to a buck stage.
CS1630/31 Figure 20 illustrates the tapped buck stage configured for series output mode. LED1+ VBST R15 C12 D10 LED 1C9 D8 Z3 D9 Q5 D GND R16 C10 D11 LED 2+ C11 CS1630 /31 L3 GD FBAUX FBSENSE GND 12 13 15 LED 2IGND Q4 R13 11 R11 R14 Figure 20.
CS1630/31 5.8.6 Output Open Circuit Protection Output open circuit protection and output overvoltage protection (OVP) are implemented by monitoring the output voltage through the second-stage inductor auxiliary winding. Overvoltage protection is enabled by setting bit OVP to ‘0’ in register Config47 (see "Configuration 47 (Config47) – Address 79" on page 41). If the voltage on the FBAUX pin exceeds a threshold (VOVP(th)) of 1.
CS1630/31 Figure 21 illustrates the functional block diagram when connecting an optional external NTC temperature sensor to the eOTP circuit. CS1630/31 eOTP Control VDD ICONNECT Comp_Out eOTP + - 10 VCONNECT (th) RS C NTC NTC Figure 21. eOTP Functional Diagram Current ICONNECT is generated from an 8-bit controlled current source with a full-scale current of 80A. See Equation 8: V CONNECT th I CONNECT = ------------------------------------R [Eq.
Current (ILED, Nom.) CS1630/31 100% 50% eOTP Trips and Shuts Off Lamp 0 25 95 Temperature (°C) 125 Figure 22. LED Current vs. eOTP Temperature Beyond this temperature, the IC shuts down using the mechanism discussed above.
CS1630/31 PLC Start Char Special Char 90° 90° 34° ‘01’ 34° 62° ‘10’ ‘11’ 118° 146° 90° PLC Stop Char 90° ‘00’ 146° 90° Figure 24. Power Line Calibration Mode Character Waveforms 5.10.2 PLC Program Mode Characters In order to program the CS1630/31, a set of encoded characters is built from specific phase-cut waveform patterns. Figure 24 illustrates the phase-cut waveform encoding recognized by the CS1630/31 power line calibration system.
CS1630/31 5.10.4 Register Lockout The CS1630/31 provides register lockout for security against unauthorized access to proprietary registers using the I2C or PLC communication port. A 32-bit long-word is used for password protection when accessing the OTP registers. The register lockout password can be set by programming the Lockout Key registers (see "Lockout Key (LOCK0, LOCK1, LOCK2, LOCK3) – Address 1 - 4" on page 29).
CS1630/31 R/W bit, the Block/Single (BLK/SGL) bit, and the 7-bit shadow register address. The master can then perform a read operation to retrieve the required bytes from the shadow registers. Figure 28 illustrates the protocol for a single and block read operation. whether data transfer is a read or write operation. This bit should be set to '0' to perform a write operation and '1' to perform a read operation. The 7-bit device address is the 7 most significant bit of the slave address.
CS1630/31 Data Transferred (1 Byte and Acknowledge) Slave Address (1 Byte and Acknowledge) S Device Address (7-bit) Start Condition 0 A ‘0’ = Write Register Address (7-bit) 0 Device Address (7-Bit) Start Condition 0 A P Stop Condition Data Transferred (n Bytes and Acknowledge) A ‘0’ = Write Data ‘A’ = Acknowledge (SDA Low) ‘0’ = Single Slave Address (1 Byte and Acknowledge) S A 1 ‘1’ = Block Register Address (7-Bit) A Data A … ...
CS1630/31 5.12 OTP Memory At startup, the contents of the OTP memory are read into shadow registers that make up a register file. Access to the OTP memory values is accomplished by reading and writing to the OTP corresponding address locations in that register file. To program the part, each unprogrammed address location must be filled with an appropriate value. Next, a CRC is calculated corresponding to the OTP space that is being programmed.
CS1630/31 6. ONE-TIME PROGRAMMABLE (OTP) REGISTERS 6.
CS1630/31 49 50 51 0x31 0x32 0x33 Config17 Config18 PEAK_CUR Configuration 17 Configuration 18 Peak Current .... ............. - Reserved 70 0x46 Config38 Configuration 38 .... .............
CS1630/31 6.2 Configuration 0 (Config0) – Address 0 7 - 6 - 5 - Number Name [7:2] - [1] MODE [0] LOCKOUT 4 - 3 - 2 - 1 MODE 0 LOCKOUT Description Reserved Appends two of the color system coefficients (P01 followed by P10) to the 32bit lockout key to make it a 64-bit key from a 32-bit key to increase security. 0 = 32-bit key 1 = 64-bit key Configures the IC lockout security mechanism by using Lockout Key. 0 = Disable 1 = Enable 6.
CS1630/31 6.5 Color Polynomial Coefficient (Q3, Q2, Q1, Q0) – Address 25 - 32 MSB 3 -(2 ) 14 13 12 11 10 2 1 0 -1 -2 2 2 2 2 2 9 8 7 6 5 4 3 2 1 LSB -3 -4 -5 -6 -7 -8 -9 -10 -11 2-12 2 2 2 2 2 2 2 2 2 Coefficients of the color polynomial used to calculate the gain (GAINDR) that controls the current in the white LED channel based on the current dim level. The value is a two's complement number in the range of -8.0value<8.
CS1630/31 6.7 Configuration 2 (Config2) – Address 34 7 CLAMP1 Number [7:6] 6 CLAMP0 5 T2COMP Name CLAMP[1:0] 4 - 3 - 2 - 1 VALLEYSW 0 - Description Configures the offset adjustment for the minimum measurable peak current level on the second stage sense resistor when the gate drive is turned on. CLAMP[1:0] is an unsigned integer in the range of 0value3.
CS1630/31 6.8 Configuration 3 (Config3) – Address 35 7 STRING 6 TT_MAX1 Number Name [7] STRING [6:5] [4] [3:1] 5 TT_MAX0 4 LED_ARG 3 IPEAK2 2 IPEAK1 1 IPEAK0 0 - Description Configures second stage series/parallel output channel configuration. 0 = Second stage configured as parallel strings 1 = Second stage configured with strings in series Configures the maximum measurable second stage switching cycle period. 00 = 51.15s TT_MAX[1:0] 01 = 102.35s 10 = 153.55s 11 = 204.
CS1630/31 6.9 Configuration 4 (Config4) – Address 36 7 6 5 4 3 2 T2CH1GAIN5 T2CH1GAIN4 T2CH1GAIN3 T2CH1GAIN2 T2CH1GAIN1 T2CH1GAIN0 Number [7:2] Name T2CH1GAIN[5:0] 1 SYNC 0 POL_ZCD Description Sets T2 compensation gain T2CH1CompGain for channel 1, which is required when T2 measurement compensation is enabled for flyback designs. The value is an unsigned integer in the range of 0T2CH1GAIN[5:0]<63.
CS1630/31 6.12 Configuration 7 (Config7) – Address 39 7 PROBE Number [7] 6 PRCNT3 5 PRCNT2 4 PRCNT1 Name 3 PRCNT0 2 - 1 - 0 - Description Configures the automated TRES probe operation that measures the resonant frequency on the drain of the second stage FET using the reflected voltage applied to the FBAUX pin for improved valley switching performance.
CS1630/31 6.14 Channel 1 Output Current (CH1CUR) – Address 41 7 2 6 7 2 5 6 2 5 4 2 3 4 2 2 3 2 2 1 2 1 0 20 CH1CUR sets the target output current for channel 1. The register value plus bit CH1CURMSB forms an unsigned integer in the range of 0value511. 6.15 Configuration 10 (Config10) – Address 42 7 BUCK3 6 BUCK2 Number [7:4] [3:1] 5 BUCK1 4 BUCK0 3 RE1_ZCD2 Name BUCK[3:0] 2 RE1_ZCD1 1 RE1_ZCD0 0 CH2CURMSB Description Configures buck topology.
CS1630/31 6.17 Configuration 12 (Config12) – Address 44 7 TIMEOUT1 Number [7:6] 6 TIMEOUT0 5 S2CONFIG 4 DITATT1 3 DITATT0 Name 2 - 1 - 0 - Description Sets the T2 time-out limit to ensure a minimum switching frequency for each channel. 00 = 45ms TIMEOUT[1:0] 01 = 70.6ms 10 = 96.2ms 11 = 121.8ms S2CONFIG Configures second stage for flyback or buck/tapped buck.
CS1630/31 6.20 Configuration 15 (Config15) – Address 47 7 EXIT_PH3 Number 6 EXIT_PH2 5 EXIT_PH1 4 EXIT_PH0 3 DECL_PH3 2 DECL_PH2 1 DECL_PH1 0 DECL_PH0 Name Description [7:4] EXIT_PH[3:0] Configures the number of channel 1 switching periods between phase synchronization conditions on the second stage. EXIT_PH[3:0] provides a hysteresis to prevent consecutive resynchronizations by the controller. The value is an unsigned integer in the range of 0value15.
CS1630/31 6.22 Configuration 17 (Config17) – Address 49 7 DITHER 6 RESYNC 5 4 3 2 1 0 T2CH2GAIN5 T2CH2GAIN4 T2CH2GAIN3 T2CH2GAIN2 T2CH2GAIN1 T2CH2GAIN0 Number Name [7] DITHER Configures dither on the second stage primary side peak current threshold. 0 = Disable dither 1 = Enable dither RESYNC Configures resynchronization of a dual channel second stage design where the channel synchronization circuit is not directly driven from the SYNC pin.
CS1630/31 6.24 Peak Current (PEAK_CUR) – Address 51 7 2 6 7 2 5 6 2 5 4 2 4 3 2 3 2 2 2 1 2 1 0 20 PEAK_CUR sets the boost stage peak current, which assists in configuring the boost output power. The register value is an unsigned integer in the range of 0value255 where the LSB = 4.1mA.The peak current can be configured from 0mA to 1.0455A. 6.
CS1630/31 6.27 Configuration 45 (Config45) – Address 77 7 - 6 - 5 - 4 - 3 - 2 - 1 VDIFF_LAT 0 MAX_CUR Number Name [7:2] - [1] VDIFF_LAT Selects if the VDiff fault is to be a latched type fault. 0 = Unlatched fault 1 = Latched fault MAX_CUR Configures the second stage to draw maximum power when the boost output voltage exceeds boost overvoltage protection threshold VBST > VBOP(th), triggering a boost overvoltage fault. 0 = Disable 1 = Enable [0] Description Reserved 6.
CS1630/31 6.29 Configuration 47 (Config47) – Address 79 7 OCP 6 OLP 5 OVP 4 BOP 3 COP 2 LLP 1 EEOTP 0 IOTP Number Name [7] OCP Configures second stage primary side overcurrent protection. 0 = Enable 1 = Disable OLP Configures second stage primary side open loop protection (RSense Short Protection). 0 = Enable 1 = Disable [5] OVP Configures second stage secondary side overvoltage protection (Output Open Circuit Protection).
CS1630/31 6.30 Configuration 48 (Config48) – Address 80 7 6 5 4 3 2 1 0 OCP_BLANK3 OCP_BLANK2 OCP_BLANK1 OCP_BLANK0 OLP_BLANK2 OLP_BLANK1 OLP_BLANK0 IOTP_SAMP Number [7:4] Name Description Configures fixed time-blanking interval tOCP for overcurrent protection OCP_BLANK[3:0] (OCP). The value is an unsigned integer in the range of 0value15. t OCP = 150ns + OCP_BLANK [3:0] 50ns [3:1] Configures fixed time blanking interval tOLP for open loop protection (OLP) and sense resistor protection.
CS1630/31 6.32 Configuration 50 (Config50) – Address 82 7 OVP_CNT2 Number 6 OVP_CNT1 5 OVP_CNT0 4 OVP_LAT 3 OVP_TYPE 2 1 0 OVP_BLANK2 OVP_BLANK1 OVP_BLANK0 Name Description [7:5] OVP_CNT[2:0] Sets the second stage OVP fault counter threshold used when declaring a fault. 0 = Force OVP fault (debug only) 1-7 = Number of times an OVP fault has to occur consecutively before the IC will enter a fault state. [4] OVP_LAT [3] [2:0] OVP_TYPE Configures second stage OVP fault type.
CS1630/31 6.34 Configuration 52 (Config52) – Address 84 7 6 5 4 3 2 1 COP_THRES6 COP_THRES5 COP_THRES4 COP_THRES3 COP_THRES2 COP_THRES1 COP_THRES0 Number [7:1] Name COP_THRES[6:0] 0 COP_INT Description Value used to determine the COP Filter Threshold. The clamp is sampled every 20s and over the selected interval is compared to COP time-on threshold, TON(th) to determine if an COP fault has occurred. For a 1 second interval: T ON th = COP_THRES [6:0] 5.12ms + 2.
CS1630/31 6.35 Configuration 53 (Config53) – Address 85 7 6 5 4 3 2 1 0 BOP_INTEG2 BOP_INTEG1 BOP_INTEG0 BOP_THRES3 BOP_THRES2 BOP_THRES1 BOP_THRES0 BOOST_ON Number [7:5] Name Description Sets the leaky integrator output threshold for declaring a boost output protection (BOP) fault. The BOP fault signal is averaged continuously using a leaky integrator and if the averaged value exceeds the leaky integrator output threshold a BOP fault is declared.
CS1630/31 6.36 Configuration 54 (Config54) – Address 86 7 LLP_TIME2 Number 5 LLP_TIME0 4 BOP_RSTART Name 3 - 2 - 1 - 0 - Description [7:5] Sets the time that the condition VBST < (VLine - VLLPMin(th)) is true to trigger a boost LLP fault. See “Configuration 62 (Config62) – Address 94” on page 50 for configuring VLLPMin(th) using bits BST_LLP[1:0]. 000 = 0ms 001 = 1ms LLP_TIME[2:0] 010 = 2ms 011 = 2.5ms 100 = 3ms 101 = 3.5ms 110 = 4ms 111 = 5ms [4] Configures boost BOP fault behavior.
CS1630/31 6.37 Configuration 55 (Config55) – Address 87 7 - 6 - 5 EOTP_FLP2 Number Name [7:6] - 4 EOTP_FLP1 3 EOTP_FLP0 2 EOTP_SLP2 1 EOTP_SLP1 0 EOTP_SLP0 Description Reserved [5:3] Sets time constant of the faster low pass filter used for filtering the coarse 8-bit ADCR temperature measurements. This filter's output is used for external overtemperature fault detection by quickly detecting if the external NTC temperature has exceeded the temperature set point TempShutdown.
CS1630/31 6.39 Configuration 58 (Config58) – Address 90 7 SHUTDWN3 6 SHUTDWN2 Number 5 SHUTDWN1 4 SHUTDWN0 3 LOW_SAT2 Name 2 LOW_SAT1 1 LOW_SAT0 0 DIM_TEMP Description Configures the 8-bit code value corresponding to temperature threshold TempShutdown. If the temperature exceeds this threshold, the device enters an external overtemperature state and shuts down.
CS1630/31 6.41 Configuration 60 (Config60) – Address 92 7 - 6 PLC 5 - Number Name [7] - [6] PLC [5] - [4:2] 4 CS_DELAY2 3 CS_DELAY1 2 CS_DELAY0 1 - 0 - Description Reserved Configures the power line calibration (PLC) mode. 0 = Enable 1 = Disable Reserved Configures the ISense comparator delay and board delays incurred through FET switching T1comp. Switching time T1comp can be set from 0ns to 350ns in CS_DELAY[2:0] steps of 50ns. T1 comp = CS_DELAY[2:0] 50ns [1:0] - Reserved 6.
CS1630/31 6.43 Configuration 62 (Config62) – Address 94 7 CH2_OFF2 Number [7:5] 6 CH2_OFF1 5 CH2_OFF0 4 CH1_OFF2 3 CH1_OFF1 Name 2 CH1_OFF0 1 BST_LLP1 0 BST_LLP0 Description Sets fixed offset delay for ZCD comparator and other path delays in order to get correct T2 measurements for channel 2. Adjusting CH2_OFF[2:0] correctly CH2_OFF[2:0] is necessary to achieve accurate and predictable output currents across the entire dimming range.
CS1630/31 6.45 Channel 1 Color Calibration 3A (CH1_CAL3A) – Address 119 7 SET_3A 6 - Number 5 4 3 2 1 0 CH1_CAL3A5 CH1_CAL3A4 CH1_CAL3A3 CH1_CAL3A2 CH1_CAL3A1 CH1_CAL3A0 Name Description [7] SET_3A [6] - [5:0] Configures the color control system to use the color calibration values in memory tag 3A. 0 = Disables the use of memory tag 3A 1 = Enables the use of memory tag 3A Reserved Channel 1 color control system calibration value that scales the current of channel 1 within ±15%.
CS1630/31 6.48 Channel 1 Color Calibration 3B (CH1_CAL3B) – Address 122 7 SET_3B 6 - Number 5 4 3 2 1 0 CH1_CAL3B5 CH1_CAL3B4 CH1_CAL3B3 CH1_CAL3B2 CH1_CAL3B1 CH1_CAL3B0 Name Description [7] SET_3B [6] - [5:0] Configures the color control system to use the color calibration values in memory tag 3B.
CS1630/31 6.51 Channel 1 Color Calibration 3C (CH1_CAL3C) – Address 125 7 SET_3C 6 - 5 4 3 2 1 0 CH1_CAL3C5 CH1_CAL3C4 CH1_CAL3C3 CH1_CAL3C2 CH1_CAL3C1 CH1_CAL3C0 Number Name [7] SET_3C [6] - [5:0] Description Configures the color control system to use the color calibration values in memory tag 3C.
CS1630/31 7. PACKAGE DRAWING 16 SOICN (150 MIL BODY WITH EXPOSED PAD) mm MIN NOM MAX MIN NOM MAX A -- -- 1.75 -- -- 0.069 A1 0.10 -- 0.25 0.004 -- 0.010 b 0.31 -- 0.51 0.012 -- 0.020 c 0.10 -- 0.25 0.004 -- 0.010 D D1 9.90BSC 4.95 5.25 0.195 0.201 E 6.00BSC 0.236BSC 3.90BSC 0.154BSC 2.35 e 54 5.10 0.390BSC E1 E2 1. 2. 3. 4. inch Dimension 2.50 2.65 0.093 1.27BSC 0.098 0.207 0.104 0.05BSC L 0.40 -- 1.27 0.016 -- 0.
CS1630/31 8. ORDERING INFORMATION Ordering Number Container CS1630-FSZ Bulk CS1630-FSZR Tape & Reel CS1631-FSZ Bulk CS1631-FSZ Tape & Reel AC Line Voltage Temperature Package Description 120VAC -40°C to +125°C 16-lead SOICN, Lead (Pb) Free 230VAC -40°C to +125°C 16-lead SOICN, Lead (Pb) Free 9. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Ratinga Max Floor Lifeb CS1630-FSZ 260°C 3 7 Days CS1631-FSZ 260°C 3 7 Days a.
CS1630/31 10.
